FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 2

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

Functional Details
General
The transmitter and receiver chip set is
optimised for transponder solutions and
Optical Network interconnects such as
bridges and gateways. The intended
transponder system is shown on page 1.
Transponder System Jitter
Specifications
The transponder system exceeds ITU-T
(recommendation G.825 for a Type B
regenerator) and Bellcore recommenda-
tions with respect to output jitter.
The jitter-tolerance on the input side ex-
ceeds ITU-T (recommendation G.958)
and Bellcore recommendations.
GD16556 - The Receiver
The GD16556 receiver integrates:
u
u
u
u
into a complete Clock Data Recovery
(CDR) system. The CDR is followed by a
1:16 de-multiplexer. A lock-detect output
monitors if the CDR is locked onto the re-
ceived serial data.
GD16557 - The Transmitter
The GD16557 transmitter is a 16:1 multi-
plexer with an integrated double PLL to-
pology requiring an external VCXO to
achieve a superior jitter clean-up.
System Speed
The pins RSEL1 and RSEL2 choose the
line rate (155 Mbit/s, 622 Mbit/s,
2.488 Gbit/s and 1.250 Gbit/s). It is the
responsibility of the system to monitor
the bit rate and assert the signals RSEL1
and RSEL2.
Bypass Data Path
To enable handling of non-compatible bit
rates a bypass data path is featured. This
path bypasses the CDR in the receiver
and the multiplexer in the transmitter.
The bypass data I/O (BP, BPN) are CML
compatible with a LVTTL compatible ac-
tive low enable pin BPEN in order to re-
duce noise at the printed circuit board
when disabled. The system needs to
monitor the incoming bit rate and assert
the BPEN signal properly.
Data Sheet Rev.: 23
a Limiting Input Amplifier (LIA)
a Bang-Bang Phase Detector
a Phase Frequency Detector
a Voltage Controlled Oscillator
Figure 1. An example configuration of a channel in a transponder system
Figure 2. The core circuit
Figure 3. Basic PLL frequency syntesis
Loop-back Data and Clock
Path
A loop-back data path is featured to en-
able easy means of fault diagnostics and
system verification etc. The loop-back
data and clock path bypasses the de-
multiplexer in the receiver and the multi-
plexer in the transmitter. The loop-back
data I/O is named LB, LBN and the
loop-back clock I/O is named LBCK,
LBCKN. To enable the loop-back paththe
system needs to assert the signal LBEN.
2.488 Gbit/s
32/31
High-speed
Reference
Clock
Data
Frequency
Referency
GD16556/GD16557*
DI/N
GD16556
F
STANDARD
DO15/N
M
DO0/N
CKO/N
GD16556 Receiver
GD16557 Transmitter
Bang-Bang
Frequency
Frequency
Frequency
Frequency
Frequency
Detector
Detector
Detector
Detector
Data
32/31 155.50 MHz
Divider
Divider
Phase
Phase
Phase
Phase
/N
/M
16
40.134 MHz
40.134 MHz
System
ASIC
The Transponder System
The chip set is designed for the tran-
sponder system shown on the front page.
The system consists of a receiver
GD16556, a system ASIC tailored for the
application and a transmitter GD16557.
Such a three-device configuration is
needed for each direction.
Appropriate timing relations are assured
by the PLL topology of the system. Fur-
thermore, the choice of PLL topology as-
VCO
VCO
VCO
16
155.50 MHz
Data
40.134 MHz
VCXO
Frequency
Divider
DI0/N
DI15/N
CNTCK/N
/N
GD16557
CKO/N
DO/N
Page 2 of 28
VCXO
2.488 Gbit/s
2.488 GHz