HBLXT9785HE.B2 Intel, HBLXT9785HE.B2 Datasheet - Page 134

• Manufacturer Part Number: HBLXT9785HE.B2
• Manufacturer: Intel

Specifications of HBLXT9785HE.B2

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 44
4.7.6
Table 45
Cortina Systems
RX Status Encoding Bit Definitions
Source Synchronous-Serial Media Independent Interface
Some system designs require the PHY to be placed between 3 to 12 inches away from
the MAC. A new Source Synchronous-Serial Media Independent Interface (SS-SMII)
definition has been added because of this requirement. To provide a source synchronous
interface between the PHY and MAC, the PHY must drive the RxCLK and the RxSYNC
signals to the MAC. Also, the MAC must drive the TxCLK and the TxSYNC signal to the
PHY. The REFCLK is also needed to synchronize the data to the PHY’s core clock
domain. TxData is clocked in using TxCLK and then synchronized to REFCLK and
transmitted to the twisted-pair. The RxData is synchronized to the RxCLK. See
on page
SS-SMII
®
CRS
RxDV
RxER
(RxData0)
SPEED
(RxData1)
DUPLEX
(RxData2)
LINK
(RxData3)
JABBER
(RxData4)
VALID
(RxData5)
False Carrier
(RxData6)
RxData7
1. Both RxData0 and RxData5 bits are valid in the segment immediately following a frame, and remain valid
TxData
TxCLK
TxSYNC
RxData
RxCLK
RxSYNC
REFCLK
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
until the first data segment of the next frame begins.
Signal
137.
PHY
PHY
PHY
MAC
MAC
MAC
MAC
To
Carrier Sense - identical to MII, except that it is not an asynchronous signal.
Receive Data Valid - identical to MII. When RX_DV = 0, status
information is transmitted to the MAC. When RX_DV = 1,
received data is transmitted to the MAC.
Inter-frame status bit RxData0 indicates whether or not the
PHY detected an error somewhere in the previous frame.
Inter-frame status bit RxData1 indicates port operating speed.
Inter-frame status bit RxData2 indicates port duplex condition.
Inter-frame status bit RxData3 indicates port link status.
Inter-frame status bit RxData4 indicates port jabber status.
Inter-frame status bit RxData5 conveys the validity of the upper
nibble of the last byte of the previous frame
Inter-frame status bit RxData6 indicates whether or not the
PHY has detected a false carrier event.
This bit is set to 1.
MAC
MAC
MAC
PHY
PHY
PHY
System
From
Transmit data & control
Transmit clock
Synchronization pulses
Receive data & control
Receive clock
Receive Synchronization
Synchronization
Purpose
Definition
4.7 Serial MII Operation
0 = Status Byte
1 = Valid Data Byte
0 = No Error
1 = Error
0 = 10 Mbps
1 = 100 Mbps
0 = Half-duplex
1 = Full-duplex
0 = Down
1 = Up
0 = OK
1 = Error
0 = Invalid
1 = Valid
0 = No FC detected
1 = FC detected
1 = Always
Figure 23
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