HBLXT9785HE.B2 Intel, HBLXT9785HE.B2 Datasheet - Page 160

• Manufacturer Part Number: HBLXT9785HE.B2
• Manufacturer: Intel

Specifications of HBLXT9785HE.B2

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Note:
Cortina Systems
Link Hold-Off is enabled on a per port basis by software control using the following two
methods:
Method One:
This method requires that Link Hold-Off is enabled by the LINKHOLD pin during the last
power-up or hardware reset.
Method Two:
This method enables Link Hold-Off regardless of the LINKHOLD hardware configuration
state.
High is defined by the IO voltage supply level selected (2.5V or 3.3V).
®
5. Clear Register Bit 0.11, power-down for each individual port.
6. Normal operation resumes on each port after Register bit 0.11 is cleared (see Table
1. Set Register bit 0.15 to reset and re-enable Link Hold-Off for the desired port.
2. Program the PHY to the desired configuration.
3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off.
4. Normal operation resumes.
1. Set Register bit 0.11(power-down) to enable Link Hold-Off for the desired port.
2. Program the PHY to the desired configuration.
3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off.
4. Normal operation resumes.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
83 for the recovery time).
4.14 Link Hold-Off Overview
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