HBLXT9785HE.B2 Intel, HBLXT9785HE.B2 Datasheet - Page 137

• Manufacturer Part Number: HBLXT9785HE.B2
• Manufacturer: Intel

Specifications of HBLXT9785HE.B2

• Lead Free Status / RoHS Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Figure 22
Figure 23
4.8
Note:
4.8.1
Cortina Systems
SS-SMII Transmit Timing
SS-SMII Receive Timing
RMII Operation
The LXT9785/LXT9785E provides an independent Reduced MII port for each network
port. Each RMII uses four signals to pass received data to the MAC: RxDatan<1:0>,
RxERn, and CRS_DVn (where n reflects the port number). Three signals are used to
transmit data from the MAC: TxDatan_<1:0> and TxENn. Both receive and transmit
signals are clocked by REFCLK. Data transmission across the RMII is implemented in di-
bit pairs which equal a 4-bit wide nibble.
The BGA15 package does not support the RMII interface.
RMII Reference Clock
The LXT9785/LXT9785E requires a 50 MHz reference clock (REFCLK). The device
samples the RMII input signals on the rising edge of REFCLK and drives RMII output
signals on the falling edge.
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
TxSYNC
TxSYNC
TxCLK
TxData
TxCLK
TxData
All signals are synchronous to the clock
RxCLK
RxData
RxSYNC
RxCLK
All signals are synchronous to the clock
RxData
RxSYNC
TXER TXEN
TXER
CRS RXDV
CRS
TXEN
RXDV
Frcerr Speed
TXD0 TXD1
RXER Speed
RXD0 RXD1
TXD2
Dplx
RXD2
Dplx
TXD3 TXD4 TXD5
LINK
RXD3 RXD4 RXD5
LINK
Jabr
Jabr
UPnib
TXD6
RXD6
FlsCar
TXD7
RXD7
TXER
TXER
CRS
CRS
4.8 RMII Operation
Page 137