DP83848KSQ National Semiconductor, DP83848KSQ Datasheet - Page 12

• Manufacturer Part Number: DP83848KSQ
• Manufacturer: National Semiconductor

Specifications of DP83848KSQ

• Lead Free Status / RoHS Status: Not Compliant

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AN0 (LED_LINK)
AN1 (LED_SPEED)
MII_MODE (RX_DV)
LED_CFG (CRS/CRS_DV)
MDIX_EN (RX_ER)
Signal Name
S, O, PU
S, O, PU
S, O, PD
S, O, PU
S, O, PU
Type
Pin #
22
21
32
33
34
These input pins control the advertised operating mode of the de-
vice according to the following table. The value on these pins are
set by connecting them to GND (0) or V
sistors. These pins should NEVER be connected directly to
GND or VCC.
The value set at this input is latched into the DP83848K at Hard-
ware-Reset.
The float/pull-down status of these pins are latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset.
The default for DP83848K is 11 since these pins have an internal
pull-up.
MII MODE SELECT: This strapping option determines the oper-
ating mode of the MAC Data Interface. Default operation (No pull-
up) will enable normal MII Mode of operation. Strapping
MII_MODE high will cause the device to be in RMII mode of oper-
ation. Since the pin includes an internal pull-down, the default val-
ue is 0.
The following table details the configuration:
LED CONFIGURATION: This strapping option determines the
mode of operation of the LED pins. Default is Mode 1. Mode 1 and
Mode 2 can be controlled via the strap option. All modes are con-
figurable via register access.
SeeTable 3 for LED Mode Selection.
MDIX ENABLE: Default is to enable MDIX. This strapping option
disables Auto-MDIX. An external pull-down will disable Auto-
MDIX mode.
12
AN1
MII_MODE
0
0
1
1
0
1
AN0
0
1
0
1
Description
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
10BASE-T, Half-Duplex
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
MII Mode
RMII Mode
MAC Interface Mode
Advertised Mode
CC
(1) through 2.2 k re-