DP83848KSQ National Semiconductor, DP83848KSQ Datasheet - Page 52

• Manufacturer Part Number: DP83848KSQ
• Manufacturer: National Semiconductor

Specifications of DP83848KSQ

• Lead Free Status / RoHS Status: Not Compliant

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7.2.5 RMII and Bypass Register (RBR)
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.
15:6
Bit
1:0
5
4
3
2
ELAST_BUF[1:0]
RX_OVF_STS
RX_UNF_STS
RMII_REV1_0
RMII_MODE
RESERVED
Bit Name
Table 25. RMII and Bypass Register (RBR), addresses 0x17
Strap, RW
Default
0,
0,
1, RW
0, RO
0
, RO
RW
RO
RESERVED: Writes ignored, Read as 0.
Reduced MII Mode:
0 = Standard MII Mode
1 = Reduced MII Mode
Reduce MII Revision 1.0:
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet
to indicate deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data
is transferred. CRS_DV will not toggle at the end of a packet.
RX FIFO Over Flow Status:
0 = Normal
1 = Overflow detected
RX FIFO Under Flow Status:
0 = Normal
1 = Underflow detected
Receive Elasticity Buffer. This field controls the Receive Elastic-
ity Buffer which allows for frequency variation tolerance between
the 50MHz RMII clock and the recovered data. The following value
indicate the tolerance in bits for a single packet. The minimum set-
ting allows for standard Ethernet frame sizes at +/-50ppm accuracy
for both RMII and Receive clocks. For greater frequency tolerance
the packet lengths may be scaled (i.e. for +/-100ppm, the packet
lengths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
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Description