DP83848KSQ National Semiconductor, DP83848KSQ Datasheet - Page 76

• Manufacturer Part Number: DP83848KSQ
• Manufacturer: National Semiconductor

Specifications of DP83848KSQ

• Lead Free Status / RoHS Status: Not Compliant

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8.2.25 RMII Receive Timing
Note: Per the RMII Specification, output delays assume a 25pF load.
Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may
toggle synchronously at the end of the packet to indicate CRS deassertion.
Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of
receive data.
Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
Note: CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of
CRS_DV.
Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the
Elasticity Buffer set to the default value (01).
T2.25.1
T2.25.2
T2.25.3
T2.25.4
T2.25.5
Parameter
PMD Input Pair
RXD[1:0]
RX_ER
RX_DV
CRS_DV
X1
X1 Clock Period
RXD[1:0], CRS_DV, RX_DV,
and RX_ER output delay from
X1 rising
CRS ON delay
CRS OFF delay
RXD[1:0] and RX_ER latency
T2.25.3
IDLE
Description
(J/K)
T2.25.2
Data
50 MHz Reference Clock
From JK symbol on PMD Receive Pair to
initial assertion of CRS_DV
From TR symbol on PMD Receive Pair to
initial deassertion of CRS_DV
From symbol on Receive Pair. Elasticity
buffer set to default value (01)
T2.25.5
76
T2.25.2
Notes
T2.25.1
(TR)
T2.25.4
T2.25.2
Data
Min
2
T2.25.2
18.5
Typ
20
27
38
Max
14
Units
bits
bits
bits
ns
ns