DP83848KSQ National Semiconductor, DP83848KSQ Datasheet - Page 21

• Manufacturer Part Number: DP83848KSQ
• Manufacturer: National Semiconductor

Specifications of DP83848KSQ

• Lead Free Status / RoHS Status: Not Compliant

RMII mode requires a 50 MHz oscillator be connected to
the device X1 pin. A 50 MHz crystal is not supported.
To tolerate potential frequency differences between the 50
MHz reference clock and the recovered receive clock, the
receive RMII function includes a programmable elasticity
buffer. The elasticity buffer is programmable to minimize
propagation delay based on expected packet size and
clock accuracy. This allows for supporting a range of
packet sizes including jumbo frames.
3.3 802.3U MII SERIAL MANAGEMENT INTER-
FACE
3.3.1 Serial Management Register Access
The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are acces-
sible through the management interface pins MDC and
MDIO. The DP83848K implements all the required MII reg-
isters as well as several optional registers. These registers
are fully described in Section 7.0. A description of the serial
management access protocol follows.
3.3.2 Serial Management Access Protocol
The serial control interface consists of two pins, Manage-
ment Data Clock (MDC) and Management Data Input/Out-
put (MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame for-
mat is shown below in Table 5..
The MDIO pin requires a pull-up resistor (1.5 k ) which,
during IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the station management entity
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83848K with a sequence that can be used
to establish synchronization. This preamble may be gener-
ated either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pull-up resis-
tor to pull the MDIO pin high during which time 32 MDC
clock cycles are provided. In addition, 32 MDC clock cycles
Read Operation
Write Operation
MII Management
Start Threshold
Serial Protocol
3 (12-bits)
0 (16-bits)
RBR[1:0]
1 (4-bits)
2 (8-bits)
Table 4. Supported packet sizes at +/-50ppm +/-100ppm for each clock
Latency Tolerance
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
10 bits
14 bits
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
2 bits
6 bits
Table 5. Typical MDIO Frame Format
Recommended Packet Size
21
The elasticity buffer will force Frame Check Sequence
errors for packets which overrun or underrun the FIFO.
Underrun and Overrun conditions can be reported in the
RMII and Bypass Register (RBR). The following table indi-
cates how to program the elasticity buffer fifo (in 4-bit incre-
ments) based on expected max packet size and clock
accuracy. It assumes both clocks (RMII Reference clock
and far-end Transmitter clock) have the same accuracy.
should be used to re-sync the device if an invalid start,
opcode, or turnaround bit is detected.
The DP83848K waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83848K serial management port has been ini-
tialized no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid con-
tention during a read transaction, no device shall actively
drive the MDIO signal during the first bit of Turnaround.
The addressed DP83848K drives the MDIO with a zero for
the second bit of turnaround and follows this with the
required data. Figure 4 shows the timing relationship
between MDC and the MDIO as driven/received by the Sta-
tion (STA) and the DP83848K (PHY) for a typical register
read access.
For write transactions, the station management entity
writes data to the addressed DP83848K thus eliminating
the requirement for MDIO Turnaround. The Turnaround
time is filled by the management entity by inserting <10>.
Figure 5 shows the timing relationship for a typical MII reg-
ister write access.
at +/- 50ppm
12000 bytes
16800 bytes
2400 bytes
7200 bytes
Recommended Packet Size
at +/- 100ppm
1200 bytes
3600 bytes
6000 bytes
8400 bytes
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