XC5VLX30-1FFG324C Xilinx Inc, XC5VLX30-1FFG324C Datasheet - Page 102
XC5VLX30-1FFG324C
Manufacturer Part Number
XC5VLX30-1FFG324C
Description
FPGA, VIRTEX-5 LX, 30K, 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FFG324C
No. Of Logic Blocks
4800
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
1179648
No. Of I/o's
220
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1558
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Chapter 3: Phase-Locked Loops (PLLs)
102
Counter Control
The PLL output counters provide a wide variety of synthesized clock using a combination
of DIVIDE, DUTY_CYCLE, and PHASE.
impact the counter output.
The top waveform represents either the output from the VCO in PLL mode.
X-Ref Target - Figure 3-6
DUTY_CYCLE = 0.75
DUTY_CYCLE = 0.33
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
DUTY_CYCLE = 0.5
Counter Clock Input
PHASE = 180
PHASE = 180
PHASE = 360
DIVIDE = 2
PHASE = 0
DIVIDE = 2
DIVIDE = 2
DIVIDE = 1
PHASE = 0
DIVIDE = 1
DIVIDE = 3
PHASE = 0
DIVIDE = 3
PHASE = 0
(VCO)
Figure 3-6: Output Counter Clock Synthesis Examples
www.xilinx.com
Figure 3-6
illustrates how the counter settings
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_3_06_041406
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