XC5VLX30-1FFG324C Xilinx Inc, XC5VLX30-1FFG324C Datasheet - Page 205

• Manufacturer Part Number: XC5VLX30-1FFG324C
• Description: FPGA, VIRTEX-5 LX, 30K, 324FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX30-1FFG324C

• No. Of Logic Blocks: 4800
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 1179648
• No. Of I/o's: 220
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Number Of I /o: 220
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1558

Table 5-8: Distributed RAM Timing Parameters
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Sequential Delays for a Slice LUT Configured as RAM (Distributed RAM)
Setup and Hold Times for a Slice LUT Configured as RAM (Distributed RAM)
Clock CLK
Notes:
1. This parameters includes a LUT configured as a two-bit distributed RAM.
2. T
3. Parameter includes AI/BI/CI/DI configured as a data input (DI2).
T
T
T
T
T
T
T
ACK
SHCKO
DS
WS
WPH
WPL
WC
XXCK
/T
/T
/T
DH
WH
(1)
CKA
= Setup Time (before clock edge), and T
(3)
Parameter
Distributed RAM Timing Parameters
Table 5-8
of the paths in
shows the timing parameters for the distributed RAM in SLICEM for a majority
AX/BX/CX/DX configured as
data input (DI1)
A/B/C/D address inputs
WE input
CLK to A/B/C/D outputs
Figure
CKXX
Function
5-27.
= Hold Time (after clock edge).
www.xilinx.com
Time after the CLK of a write operation that the
data written to the distributed RAM is stable on
the A/B/C/D output of the slice.
Time before/after the clock that data must be
stable at the AX/BX/CX/DX input of the slice.
Time before/after the clock that address signals
must be stable at the A/B/C/D inputs of the slice
LUT (configured as RAM).
Time before/after the clock that the write enable
signal must be stable at the WE input of the slice
LUT (configured as RAM).
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write
cycle time.
(2)
Description
CLB / Slice Timing Models
205