PIC12LF1822T-I/SN Microchip Technology, PIC12LF1822T-I/SN Datasheet - Page 131
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PIC12LF1822T-I/SN
Manufacturer Part Number
PIC12LF1822T-I/SN
Description
3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Na
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Specifications of PIC12LF1822T-I/SN
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
PIC12LF
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1822T-I/SN
Manufacturer:
MICROCHIP
Quantity:
3 900
- Current page: 131 of 404
- Download datasheet (4Mb)
REGISTER 13-1:
REGISTER 13-2:
REGISTER 13-3:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
U-0
U-0
U-0
—
—
—
Unimplemented: Read as ‘0’
IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt
0 = Interrupt-on-Change disabled for the associated pin.
Unimplemented: Read as ‘0’
IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt
0 = Interrupt-on-Change disabled for the associated pin.
Unimplemented: Read as ‘0’
IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin.
0 = No change was detected, or the user cleared the detected change.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge
was detected on RAx.
flag will be set upon detecting an edge.
flag will be set upon detecting an edge.
U-0
U-0
U-0
—
—
—
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W/HS-0/0
IOCAN5
R/W-0/0
IOCAP5
R/W-0/0
IOCAF5
PIC12F/LF1822/PIC16F/LF1823
R/W/HS-0/0
R/W-0/0
IOCAP4
R/W-0/0
IOCAN4
IOCAF4
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
R/W/HS-0/0
IOCAN3
R/W-0/0
IOCAP3
R/W-0/0
IOCAF3
R/W/HS-0/0
R/W-0/0
IOCAP2
R/W-0/0
IOCAN2
IOCAF2
R/W/HS-0/0
IOCAN1
R/W-0/0
IOCAP1
R/W-0/0
IOCAF1
DS41413B-page 131
R/W/HS-0/0
R/W-0/0
IOCAP0
R/W-0/0
IOCAN0
IOCAF0
bit 0
bit 0
bit 0
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