PIC18F43K20-E/MV Microchip Technology, PIC18F43K20-E/MV Datasheet - Page 280

• Manufacturer Part Number: PIC18F43K20-E/MV
• Description: 8KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TUB
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F43K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC18F2XK20/4XK20
FIGURE 20-3:
DS41303G-page 280
FIGURE 20-2:
FVR
C1RSEL
CV
FVR
CV
C2RSEL
REF
REF
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C1IN+
C2IN+
C1CH<1:0>
C2CH<1:0>
0
1
0
1
MUX
MUX
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C1V
C2V
C1R
C2R
0
1
2
3
0
1
REF
REF
Note 1:
0
1
MUX
0
1
2
3
2
MUX
Note 1:
MUX
2
MUX
2:
3:
4:
2:
3:
4:
C2V
C2V
When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
Output shown for reference only. See I/O port pin block diagram for more detail.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
C1V
C1V
When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
Output shown for reference only. See I/O port pin block diagram for more detail.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
C2SP
IN
IN
C1SP
IN
IN
-
+
-
+
C2
+
-
C2ON
C1
C1ON
C2POL
(1)
C1POL
(1)
Q3*RD_CM2CON0
Q3*RD_CM1CON0
Q1
Q1
NRESET
C2OUT
D
EN
Reset
D
EN
C1OUT
Q
Q
D
EN
CL
D
EN
CL
Q
Q
 2010 Microchip Technology Inc.
OSC
RD_CM2CON0
OSC
RD_CM1CON0
C2OE
).
To PWM Logic
).
To PWM Logic
C1OE
Data Bus
Set C2IF
C2OUT pin
Data Bus
Set C1IF
C1OUT pin
To
To
(2)
(2)