PIC18F86J90T-I/PT Microchip Technology, PIC18F86J90T-I/PT Datasheet - Page 119

• Manufacturer Part Number: PIC18F86J90T-I/PT
• Description: Segmented LCD, 96KB Flash, 4KB RAM, 12 MIPS, NanoWatt 80 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 10-3:
TABLE 10-4:
 2010 Microchip Technology Inc.
RA0/AN0
RA1/AN1/SEG18
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI/
SEG14
RA5/AN4/SEG15
OSC2/CLKO/RA6
Legend:
PORTA
LATA
TRISA
ADCON1
LCDSE1
LCDSE2
Legend:
Note 1:
OSC1/CLKI/RA7
Name
Pin Name
REF
REF
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
— = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are
disabled and read as ‘x’.
TRISA7
TRIGSEL
LATA7
RA7
-
+
SE15
SE23
Bit 7
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
PORTA FUNCTIONS
(1)
(1)
Function
SEG18
SEG14
SEG15
V
T0CKI
OSC2
CLKO
OSC1
V
CLKI
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
RA7
REF
REF
TRISA6
LATA6
RA6
SE14
SE22
+
Bit 6
-
—
(1)
(1)
(1)
Setting
TRIS
0
1
1
0
1
1
x
0
1
1
1
0
1
1
1
0
1
x
x
0
1
1
x
x
x
0
1
x
x
0
1
TRISA5
VCFG1
LATA5
SE13
SE21
Bit 5
RA5
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
TRISA4
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
VCFG0
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
TTL
LATA4
I/O
ST
ST
SE12
SE20
Bit 4
RA4
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
LCD Segment 18 output; disables all other pin functions.
LATA<2> data output; not affected by analog input.
PORTA<2> data input; disabled when analog functions enabled.
A/D Input Channel 2. Default input configuration on POR.
A/D and comparator low reference voltage input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D Input Channel 3. Default input configuration on POR.
A/D and comparator high reference voltage input.
LATA<4> data output.
PORTA<4> data input. Default configuration on POR.
Timer0 clock input.
LCD Segment 14 output; disables all other pin functions.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D Input Channel 4. Default configuration on POR.
LCD Segment 15 output; disables all other pin functions.
Main oscillator feedback output connection (HS and HSPLL modes).
System cycle clock output (F
LATA<6> data output; disabled when FOSC2 Configuration bit is set.
PORTA<6> data input; disabled when FOSC2 Configuration bit is set.
Main oscillator input connection (HS and HSPLL modes).
Main external clock source input (EC and ECPLL modes).
LATA<7> data output; disabled when FOSC2 Configuration bit is set.
PORTA<7> data input; disabled when FOSC2 Configuration bit is set.
TRISA3
PCFG3
LATA3
SE11
SE19
Bit 3
RA3
PIC18F87J90 FAMILY
TRISA2
PCFG2
LATA2
SE10
SE18
Bit 2
RA2
Description
OSC
TRISA1
PCFG1
LATA1
SE09
SE17
Bit 1
RA1
/4) (EC and ECPLL modes).
TRISA0
PCFG0
LATA0
SE08
SE16
Bit 0
RA0
DS39933D-page 119
Reset Values
on page
63
62
62
61
61
61