PIC18F96J60-I/PF Microchip Technology, PIC18F96J60-I/PF Datasheet - Page 149
![64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F96J60-I/PF
Manufacturer Part Number
PIC18F96J60-I/PF
Description
64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
Specifications of PIC18F96J60-I/PF
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F96J60-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- Current page: 149 of 480
- Download datasheet (8Mb)
TABLE 10-9:
© 2009 Microchip Technology Inc.
RD0/AD0/PSP0
(RD0/P1B)
RD1/AD1/PSP1
(RD1/ECCP3/
P3A)
RD2/AD2/PSP2
(RD2/CCP4/
P3D)
RD3/AD3/
PSP3
RD4/AD4/
PSP4/SDO2
Legend:
Note 1:
Pin Name
(1)
2:
3:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
These features or port pins are implemented only on 100-pin devices.
External memory interface I/O takes priority over all other digital and PSP I/O.
These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with
RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D).
(1)
ECCP3
Function
SDO2
PSP0
PSP1
PSP2
CCP4
PSP3
PSP4
PORTD FUNCTIONS
RD3
RD4
AD0
P1B
AD1
P3A
AD2
P3D
AD3
AD4
RD0
RD1
RD2
(1)
(3)
(1)
(3)
(1)
(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(3)
(1)
(3)
Setting
TRIS
0
1
x
x
x
x
0
0
1
x
x
x
x
0
1
0
0
1
x
x
x
x
0
1
0
0
1
x
x
x
x
0
1
x
x
x
x
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
DIG
TTL
DIG
DIG
DIG
TTL
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
LATD<0> data output.
PORTD<0> data input; weak pull-up when RDPU bit is set.
External memory interface, address/data bit 0 output.
External memory interface, data bit 0 input.
PSP read output data (LATD<0>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATD<1> data output.
PORTD<1> data input; weak pull-up when RDPU bit is set.
External memory interface, address/data bit 1 output.
External memory interface, data bit 1 input.
PSP read output data (LATD<1>); takes priority over port data.
PSP write data input.
ECCP3 compare and PWM output; takes priority over port data.
ECCP3 capture input.
ECCP3 Enhanced PWM output, channel A; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATD<2> data output.
PORTD<2> data input; weak pull-up when RDPU bit is set.
External memory interface, address/data bit 2 output.
External memory interface, data bit 2 input.
PSP read output data (LATD<2>); takes priority over port data.
PSP write data input.
CCP4 compare output and PWM output; takes priority over port data.
CCP4 capture input.
ECCP3 Enhanced PWM output, channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATD<3> data output.
PORTD<3> data input; weak pull-up when RDPU bit is set.
External memory interface, address/data bit 3 output.
External memory interface, data bit 3 input.
PSP read output data (LATD<3>); takes priority over port data.
PSP write data input.
LATD<4> data output.
PORTD<4> data input; weak pull-up when RDPU bit is set.
External memory interface, address/data bit 4 output.
External memory interface, data bit 4 input.
PSP read output data (LATD<4>); takes priority over port data.
PSP write data input.
SPI data output (MSSP2 module); takes priority over port data.
PIC18F97J60 FAMILY
Description
(2)
(2)
(2)
(2)
(2)
DS39762E-page 149
(2)
(2)
(2)
(2)
(2)
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