PIC18F96J60-I/PF Microchip Technology, PIC18F96J60-I/PF Datasheet - Page 269
![64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F96J60-I/PF
Manufacturer Part Number
PIC18F96J60-I/PF
Description
64KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
Specifications of PIC18F96J60-I/PF
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F96J60-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- Current page: 269 of 480
- Download datasheet (8Mb)
19.4
The MSSP module in I
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCLx) – RC3/SCK1/SCL1
• Serial data (SDAx) – RC4/SDI1/SDA1
The user must configure these pins as inputs by setting
the TRISC<4:3> or TRISD<5:4> bits.
FIGURE 19-7:
© 2009 Microchip Technology Inc.
(or RD6/SCK2/SCL2 for 100-pin devices)
(or RD5/SDI2/SDA2 for 100-pin devices)
SDAx
SCLx
I
2
C Mode
Read
Shift
Clock
MSb
Stop bit Detect
Address Mask
SSPxADD reg
Match Detect
SSPxBUF reg
SSPxSR reg
MSSP BLOCK DIAGRAM
(I
Start and
2
2
C mode fully implements all
C™ MODE)
LSb
Write
Addr Match
Set, Reset
S, P bits
(SSPxSTAT reg)
Internal
Data Bus
PIC18F97J60 FAMILY
19.4.1
The MSSP module has six registers for I
These are:
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Control Register 2 (SSPxCON2)
• MSSPx Status Register (SSPxSTAT)
• MSSPx Receive Buffer/Transmit Register
• MSSPx Shift Register (SSPxSR) – Not directly
• MSSPx Address Register (SSPxADD)
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I
SSPxCON1 and SSPxCON2 registers are readable
and writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
Many of the bits in SSPxCON2 assume different
functions, depending on whether the module is operat-
ing in Master or Slave mode. SSPxCON2<5:1> also
assume different names in Slave mode. The different
aspects of SSPxCON2 are shown in Register 19-5 (for
Master mode) and Register 19-6 (Slave mode).
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data bytes
are written to or read from.
SSPxADD register holds the slave device address when
the MSSP is configured in I
MSSP is configured in Master mode, the lower seven
bits of SSPxADD act as the Baud Rate Generator reload
value.
In receive operations, SSPxSR and SSPxBUF together
create a double-buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
(SSPxBUF)
accessible
transmission,
REGISTERS
the
2
C Slave mode. When the
2
C mode operation. The
SSPxBUF
DS39762E-page 269
2
C operation.
is
not
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