PIC18LF25K22-E/SS Microchip Technology, PIC18LF25K22-E/SS Datasheet - Page 375
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF25K22-E/SS
Manufacturer Part Number
PIC18LF25K22-E/SS
Description
32KB, Flash, 1536bytes-RAM,8-bit Family,nanoWatt XLP 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF25K22-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF25K22-E/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
AND W with f
ANDWF
0 f 255
d [0,1]
a [0,1]
(W) .AND. (f) dest
N, Z
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
ANDWF
Read
0001
Q2
17h
C2h
02h
C2h
f {,d {,a}}
01da
REG, 0, 0
Process
Data
Q3
ffff
for details.
destination
Write to
Q4
ffff
Preliminary
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
PIC18(L)F2X/4XK22
Before Instruction
After Instruction
operation
Decode
Decode
PC
If CARRY
If CARRY
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Carry
BC
-128 n 127
if CARRY bit is ‘1’
(PC) + 2 + 2n PC
None
If the CARRY bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
=
=
n
address (HERE)
1;
address (HERE + 12)
0;
address (HERE + 2)
0010
BC
operation
Process
Process
Data
Data
Q3
No
Q3
DS41412D-page 375
5
nnnn
Write to PC
operation
operation
Q4
Q4
No
No
nnnn
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