PIC18LF25K22-E/SS Microchip Technology, PIC18LF25K22-E/SS Datasheet - Page 98
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PIC18LF25K22-E/SS
Manufacturer Part Number
PIC18LF25K22-E/SS
Description
32KB, Flash, 1536bytes-RAM,8-bit Family,nanoWatt XLP 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF25K22-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF25K22-E/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18(L)F2X/4XK22
6.2.2
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.3
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte,
Table Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations on the TBLPTR
affect only the low-order 21 bits.
6.2.4
TBLPTR is used in reads, writes and erases of the
Flash program memory.
TABLE 6-1:
FIGURE 6-3:
DS41412D-page 98
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
Example
Note 1: n = 6 for block sizes of 64 bytes.
21
TABLAT – TABLE LATCH REGISTER
TBLPTR – TABLE POINTER
REGISTER
TABLE POINTER BOUNDARIES
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
TBLPTRU
TABLE POINTER BOUNDARIES BASED ON OPERATION
16
15
TABLE ERASE/WRITE
TBLPTR<21:n+1>
TBLPTR is incremented before the read/write
TBLPTR is decremented after the read/write
TABLE READ – TBLPTR<21:0>
TBLPTR is incremented after the read/write
TBLPTRH
Preliminary
Operation on Table Pointer
(1)
TBLPTR is not modified
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
directly into the TABLAT register.
When a TBLWT is executed the byte in the TABLAT
register is written, not to Flash memory but, to a holding
register in preparation for a program memory write. The
holding registers constitute a write block which varies
depending on the device (see
LSbs of the TBLPTRL register determine which specific
address within the holding register block is written to.
The MSBs of the Table Pointer have no effect during
TBLWT operations.
When a program memory write is executed the entire
holding register block is written to the Flash memory at
the address determined by the MSbs of the TBLPTR.
The 3, 4, or 5 LSBs are ignored during Flash memory
writes. For more detail, see
Flash Program
When an erase of program memory is executed, the
16 MSbs
(TBLPTR<21:6>) point to the 64-byte block that will be
erased. The Least Significant bits (TBLPTR<5:0>) are
ignored.
Figure 6-3
TBLPTR based on Flash program memory operations.
8
7
describes the relevant boundaries of
of
Memory”.
the
TBLPTRL
2010 Microchip Technology Inc.
TBLPTR<n:0>
Table
TABLE WRITE
Section 6.5 “Writing to
Table
Pointer
6-1).The 3, 4, or 5
(1)
0
register
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