PIC18LF25K22-E/SS Microchip Technology, PIC18LF25K22-E/SS Datasheet - Page 401
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF25K22-E/SS
Manufacturer Part Number
PIC18LF25K22-E/SS
Description
32KB, Flash, 1536bytes-RAM,8-bit Family,nanoWatt XLP 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF25K22-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF25K22-E/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
REG
W
REG
W
REG
Q1
=
=
=
=
=
=
register ‘f’
Rotate Right f (No Carry)
RRNCF
0 f 255
d [0,1]
a [0,1]
(f<n>) dest<n – 1>,
(f<0>) dest<7>
N, Z
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected (default), overriding the BSR
value. If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
RRNCF
RRNCF
Read
0100
Q2
1101 0111
1110 1011
?
1101 0111
1110 1011
1101 0111
f {,d {,a}}
REG, 1, 0
REG, 0, 0
00da
Process
Data
Q3
register f
ffff
for details.
destination
Write to
Q4
ffff
Preliminary
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
PIC18(L)F2X/4XK22
Before Instruction
After Instruction
Decode
REG
REG
Q1
register ‘f’
Set f
SETF
0 f 255
a [0,1]
FFh f
None
The contents of the specified register
are set to FFh.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
SETF
Read
0110
Q2
=
=
f {,a}
5Ah
FFh
100a
Process
REG, 1
Data
Q3
DS41412D-page 401
ffff
for details.
register ‘f’
Write
Q4
ffff
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