PIC18LF25K22-E/SS Microchip Technology, PIC18LF25K22-E/SS Datasheet - Page 60
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PIC18LF25K22-E/SS
Manufacturer Part Number
PIC18LF25K22-E/SS
Description
32KB, Flash, 1536bytes-RAM,8-bit Family,nanoWatt XLP 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF25K22-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF25K22-E/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18(L)F2X/4XK22
REGISTER 4-1:
DS41412D-page 60
bit 7
Legend:
R = Readable bit
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
x = Bit is unknown
Note 1: Brown-out Reset is indicated when BOR is ‘0’ and POR is ‘1’ (assuming that both POR and BOR were set
R/W-0/0
IPEN
2:
3:
2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’.
The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and
See
to ‘1’ by firmware immediately after POR).
Power-on Resets may be detected.
Table
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: BOR Software Enable bit
If BOREN<1:0> = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN<1:0> = 00, 10 or 11:
Bit is disabled and read as ‘0’.
Unimplemented: Read as ‘0’
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware or Power-on Reset)
0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)
SBOREN
R/W-q/u
code-executed Reset occurs)
4-1.
RCON: RESET CONTROL REGISTER
Section 4.6 “Reset State of Registers”
(1)
W = Writable bit
‘0’ = Bit is cleared
u = unchanged
U-0
—
R/W-1/q
(2)
(3)
Preliminary
RI
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = depends on condition
R-1/q
TO
for additional information.
R-1/q
PD
2010 Microchip Technology Inc.
R/W-q/u
POR
(2)
R/W-0/q
BOR
bit 0
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