PIC24FJ48GA004T-I/ML Microchip Technology, PIC24FJ48GA004T-I/ML Datasheet - Page 14
![16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24FJ48GA004T-I/ML
Manufacturer Part Number
PIC24FJ48GA004T-I/ML
Description
16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ48GA004T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC24FJ16GA002-ISS PDF datasheet
- PIC24FJ16GA002-ISS PDF datasheet #2
- PIC24FJ16GA002-ISS PDF datasheet #3
- Current page: 14 of 268
- Download datasheet (2Mb)
PIC24FJ64GA004 FAMILY
TABLE 1-2:
DS39881D-page 14
CN0
CN1
CN2
CN3
CN4
CN5
CN6
CN7
CN8
CN9
CN10
CN11
CN12
CN13
CN14
CN15
CN16
CN17
CN18
CN19
CN20
CN21
CN22
CN23
CN24
CN25
CN26
CN27
CN28
CN29
CN30
CV
DISVREG
EMUC1
EMUD1
EMUC2
EMUD2
EMUC3
EMUD3
INT0
MCLR
Legend:
Note 1:
Function
REF
TTL = TTL input buffer
ANA = Analog level input/output
Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
SSOP/SOIC
SPDIP/
28-Pin
12
11
26
25
24
23
22
21
18
17
16
15
14
10
25
19
22
21
15
14
16
—
—
—
—
—
—
—
—
—
—
2
3
4
5
6
7
9
1
5
4
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
28-Pin
QFN
27
28
23
22
21
20
19
18
15
14
13
12
11
22
16
19
18
12
11
13
26
—
—
—
—
—
—
—
—
—
—
9
8
1
2
3
4
7
6
2
1
QFN/TQFP
44-Pin
34
33
19
20
21
22
23
24
25
26
27
15
14
10
44
43
42
37
38
41
36
31
30
14
21
22
42
41
43
18
11
9
8
3
2
5
4
1
6
9
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Input
ANA
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST = Schmitt Trigger input buffer
I
2
C™ = I
Interrupt-on-Change Inputs.
Comparator Voltage Reference Output.
Voltage Regulator Disable.
In-Circuit Emulator Clock Input/Output.
In-Circuit Emulator Data Input/Output.
In-Circuit Emulator Clock Input/Output.
In-Circuit Emulator Data Input/Output.
In-Circuit Emulator Clock Input/Output.
In-Circuit Emulator Data Input/Output.
External Interrupt Input.
Master Clear (device Reset) Input. This line is brought low
to cause a Reset.
2
C/SMBus input buffer
Description
2010 Microchip Technology Inc.
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