PIC24FJ48GA004T-I/ML Microchip Technology, PIC24FJ48GA004T-I/ML Datasheet - Page 144
![16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24FJ48GA004T-I/ML
Manufacturer Part Number
PIC24FJ48GA004T-I/ML
Description
16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ48GA004T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC24FJ16GA002-ISS PDF datasheet
- PIC24FJ16GA002-ISS PDF datasheet #2
- PIC24FJ16GA002-ISS PDF datasheet #3
- Current page: 144 of 268
- Download datasheet (2Mb)
PIC24FJ64GA004 FAMILY
REGISTER 15-1:
DS39881D-page 144
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6
bit 5
bit 4-2
Note 1:
SPIEN
SRMPT
R/W-0
R-0
(1)
If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4
“Peripheral Pin Select” for more information.
SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
Unimplemented: Read as ‘0’
SPIBEC2:SPIBEC0: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive
0 = SPIx Shift register is not empty
SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded. The user software has not read the previous
0 = No overflow has occurred
SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty
SISEL2:SISEL0: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when last bit is shifted into SPIxSR; as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot
011 = Interrupt when SPIx receive buffer is full (SPIRBF bit set)
010 = Interrupt when SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty
SPIROV
R/C-0
data in the SPIxBUF register.
U-0
—
(SRXMPT bit is set)
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
SRXMPT
SPISIDL
R/W-0
R/W-0
(1)
SISEL2
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SISEL1
R/W-0
U-0
—
SPIBEC2
SISEL0
R/W-0
R-0
2010 Microchip Technology Inc.
x = Bit is unknown
SPIBEC1
SPITBF
R-0
R-0
SPIBEC0
SPIRBF
R-0
R-0
bit 8
bit 0
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