PIC24FJ48GA004T-I/ML Microchip Technology, PIC24FJ48GA004T-I/ML Datasheet - Page 54
![16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24FJ48GA004T-I/ML
Manufacturer Part Number
PIC24FJ48GA004T-I/ML
Description
16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ48GA004T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC24FJ16GA002-ISS PDF datasheet
- PIC24FJ16GA002-ISS PDF datasheet #2
- PIC24FJ16GA002-ISS PDF datasheet #3
- Current page: 54 of 268
- Download datasheet (2Mb)
PIC24FJ64GA004 FAMILY
5.5.2
If a Flash location has been erased, it can be pro-
grammed using table write instructions to write an
instruction word (24-bit) into the write latch. The
TBLPAG register is loaded with the 8 Most Significant
Bytes of the Flash address. The TBLWTL and TBLWTH
EXAMPLE 5-4:
DS39881D-page 54
; Setup a pointer to data Program Memory
; Setup NVMCON for programming one word to data Program Memory
MOV
MOV
MOV
MOV
MOV
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
PROGRAMMING A SINGLE WORD
OF FLASH PROGRAM MEMORY
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
#LOW_WORD_N, W2
#HIGH_BYTE_N, W3
#0x4003, W0
W0, NVMCON
#5
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY
;
;Initialize PM Page Boundary SFR
;Initialize a register with program memory address
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
; Set NVMOP bits to 0011
; Disable interrupts while the KEY sequence is written
; Write the key sequence
; Start the write cycle
; 2 NOPs required after setting WR
;
instructions write the desired data into the write latches
and specify the lower 16 bits of the program memory
address to write to. To configure the NVMCON register
for a word write, set the NVMOP bits (NVMCON<3:0>)
to ‘0011’. The write is performed by executing the
unlock sequence and setting the WR bit (see
Example 5-4).
2010 Microchip Technology Inc.
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