PIC24FJ64GA106-E/MR Microchip Technology, PIC24FJ64GA106-E/MR Datasheet - Page 167

• Manufacturer Part Number: PIC24FJ64GA106-E/MR
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA106-E/MR

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.0
Devices in the PIC24FJ256GA110 family all feature
9 independent enhanced output compare modules.
Each of these modules offers a wide range of configu-
ration and operating options for generating pulse trains
on
Pulse-Width Modulated (PWM) waveforms for driving
power applications.
Key features of the enhanced output compare module
include:
• Hardware-configurable for 32-bit operation in all
• Synchronous and Trigger modes of output
• Two separate Period registers (a main register,
• Configurable for single pulse or continuous pulse
• Up to 6 clock sources available for each module,
14.1
14.1.1
By default, the enhanced output compare module oper-
ates in a free-running mode. The internal, 16-bit coun-
ter, OCxTMR, counts up continuously, wrapping
around from FFFFh to 0000h on each overflow, with its
period synchronized to the selected external clock
source. Compare or PWM events are generated each
time a match between the internal counter and one of
the Period registers occurs.
 2010 Microchip Technology Inc.
Note:
modes by cascading two adjacent modules
compare operation, with up to 30 user-selectable
trigger/sync sources available
OCxR, and a secondary register, OCxRS) for
greater flexibility in generating pulses of varying
widths
generation on an output event, or continuous
PWM waveform generation
driving a separate internal 16-bit counter
internal
OUTPUT COMPARE WITH
DEDICATED TIMER
General Operating Modes
Section 35. “Output Compare with
Dedicated Timer” (DS39723)
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
SYNCHRONOUS AND TRIGGER
MODES
device
Family
events,
Reference
and
can
Manual”,
produce
PIC24FJ256GA110 FAMILY
In Synchronous mode, the module begins performing
its compare or PWM operation as soon as its selected
clock source is enabled. Whenever an event occurs on
the selected sync source, the module’s internal counter
is reset. In Trigger mode, the module waits for a sync
event from another internal module to occur before
allowing the counter to run.
Free-running mode is selected by default, or any time
that the SYNCSEL bits (OCxCON2<4:0>) are set to
‘00000’. Synchronous or Trigger modes are selected
any time the SYNCSEL bits are set to any value except
‘00000’. The OCTRIG bit (OCxCON2<7>) selects
either Synchronous or Trigger mode; setting the bit
selects Trigger mode operation. In both modes, the
SYNCSEL bits determine the sync/trigger source.
14.1.2
By default, each module operates independently with
its own set of 16-Bit Timer and Duty Cycle registers. To
increase resolution, adjacent even and odd modules
can be configured to function as a single 32-bit module.
(For example, modules 1 and 2 are paired, as are
modules 3 and 4, and so on.) The odd-numbered
module (OCx) provides the Least Significant 16 bits of
the 32-bit register pairs, and the even module (OCy)
provides the Most Significant 16 bits. Wraparounds of
the OCx registers cause an increment of their
corresponding OCy registers.
Cascaded operation is configured in hardware by
setting the OC32 bits (OCxCON2<8>) for both
modules.
CASCADED (32-BIT) MODE
DS39905E-page 167