PIC24FJ64GA106-E/MR Microchip Technology, PIC24FJ64GA106-E/MR Datasheet - Page 221

• Manufacturer Part Number: PIC24FJ64GA106-E/MR
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA106-E/MR

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.0
The programmable CRC generator offers the following
features:
• User-programmable polynomial CRC equation
• Interrupt output
• Data FIFO
The module implements a software configurable CRC
generator. The terms of the polynomial and its length
can
(CRCXOR<15:1>)
(CRCCON<3:0>), respectively.
FIGURE 20-1:
 2010 Microchip Technology Inc.
Note:
be
PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
programmed
Section
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
Redundancy Check (CRC)” (DS39714).
Shift Clock (2 F
and
30.
Family
CRC BLOCK DIAGRAM
using
“Programmable
the
CY
Reference
)
the
PLEN<3:0>
X<15:1>
Manual”,
Cyclic
PIC24FJ256GA110 FAMILY
CRC Shift Engine
(8x16 or 16x8)
Variable FIFO
CRCWDAT
bits
bits
CRCDAT
Consider the CRC equation:
To program this polynomial into the CRC generator,
the CRC register bits should be set as shown in
Table
TABLE 20-1:
Note that for the value of X<15:1>, the 12th bit and the
5th bit are set to ‘1’, as required by the equation. The
0 bit required by the equation is always XORed. For a
16-bit polynomial, the 16th bit is also always assumed
to be XORed; therefore, the X<15:1> bits do not have
the 0 bit or the 16th bit.
A simplified block diagram of the module is shown in
Figure
shown in
PLEN<3:0>
Bit Name
X<15:1>
20-1.
20-1. The general topology of the shift engine is
FIFO Empty Event
Figure
20-2.
EXAMPLE CRC SETUP
x
16
+ x
12
000100000010000
+ x
5
Bit Value
Set CRCIF
+ 1
1111
DS39905E-page 221