PIC24FJ64GA106-E/MR Microchip Technology, PIC24FJ64GA106-E/MR Datasheet - Page 322

• Manufacturer Part Number: PIC24FJ64GA106-E/MR
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA106-E/MR

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GA110 FAMILY
CTMU
Customer Change Notification Service ............................ 326
Customer Notification Service .......................................... 326
Customer Support ............................................................ 326
D
Data Memory
DC Characteristics
Development Support ...................................................... 265
Device Features (Summary)
Device Overview
E
Electrical Characteristics .................................................. 269
ENVREG Pin .................................................................... 251
Equations
Errata ................................................................................... 8
F
Flash Configuration Words ................................................. 36
Flash Program Memory
DS39905E-page 322
Measuring Capacitance ........................................... 241
Measuring Time ....................................................... 242
Pulse Generation and Delay .................................... 242
Address Space ........................................................... 37
Memory Map .............................................................. 37
Near Data Space ....................................................... 38
SFR Space ................................................................. 38
Software Stack ........................................................... 53
Space Organization, Alignment ................................. 38
I/O Pin Input Specifications ...................................... 278
I/O Pin Output Specifications ................................... 279
Idle Current .............................................................. 274
Internal Voltage Regulator Specifications ................ 280
Operating Current .................................................... 273
Power-Down Current ............................................... 276
Program Memory ..................................................... 280
Temperature and Voltage Specifications ................. 271
100-Pin ....................................................................... 13
64-Pin ......................................................................... 11
80-Pin ......................................................................... 12
Core Features .............................................................. 9
Family Member Details .............................................. 10
Other Special Features .............................................. 10
Absolute Maximum Ratings ..................................... 269
Thermal Operating Conditions ................................. 270
V/F Graph ................................................................ 270
A/D Conversion Clock Period .................................. 233
Calculating the PWM Period .................................... 170
Calculation for Maximum PWM Resolution .............. 171
Computing Baud Rate Reload Value ....................... 187
Relationship Between Device and
RTCC Calibration ..................................................... 219
UART Baud Rate with BRGH = 0 ............................ 194
UART Baud Rate with BRGH = 1 ............................ 194
and Table Instructions ................................................ 57
Enhanced ICSP Operation ......................................... 58
JTAG Operation ......................................................... 58
Operations ................................................................. 58
Programming Algorithm ............................................. 60
RTSP Operation ......................................................... 58
Single-Word Programming ......................................... 63
SPI Clock Speed .............................................. 184
I
I/O Ports ........................................................................... 127
I
Input Capture
Input Capture with Dedicated Timer ................................ 163
Instruction Set
Inter-Integrated Circuit (I
Inter-Integrated Circuit. See I
Internet Address .............................................................. 326
Interrupt Controller ............................................................. 71
Interrupt Vector Table (IVT) ............................................... 71
Interrupts
J
JTAG Interface ................................................................. 255
M
Microchip Internet Web Site ............................................. 326
MPLAB ASM30 Assembler, Linker, Librarian .................. 266
MPLAB Integrated Development Environment
MPLAB PM3 Device Programmer ................................... 268
MPLAB REAL ICE In-Circuit Emulator System ............... 267
MPLINK Object Linker/MPLIB Object Librarian ............... 266
N
Near Data Space ............................................................... 38
O
Oscillator Configuration
2
C
Analog Port Configuration ........................................ 128
Configuring Analog Pins .......................................... 128
Input Change Notification ........................................ 129
Open-Drain Configuration ........................................ 128
Parallel (PIO) ........................................................... 127
Peripheral Pin Select ............................................... 129
Pull-ups and Pull-Downs .......................................... 129
Clock Rates ............................................................. 187
Communicating as Master in Single Master
Peripheral Remapping Options ................................ 185
Reserved Addresses ............................................... 187
Setting Baud Rate When Operating as
Slave Address Masking ........................................... 187
32-Bit Cascaded Mode ............................................ 164
Operations ............................................................... 164
Synchronous and Trigger Modes ............................. 163
Overview .................................................................. 259
Summary ................................................................. 257
Implemented Vectors ................................................. 73
Reset Sequence ........................................................ 71
Setup and Service Procedures ................................ 113
Trap Vectors .............................................................. 72
Vector Table .............................................................. 72
Software .................................................................. 265
Bit Values for Clock Selection .................................. 116
Clock Switching ....................................................... 120
CPU Clocking Scheme ............................................ 116
Initial Configuration on POR .................................... 116
Reference Clock Output .......................................... 122
Environment .................................................... 185
Bus Master ...................................................... 187
Sequence ........................................................ 121
2
C) ............................................ 185
 2010 Microchip Technology Inc.
2
C.