PIC24FJ64GA106T-I/PT Microchip Technology, PIC24FJ64GA106T-I/PT Datasheet
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... PIC24FJ256GA110 Family General Purpose Flash Microcontrollers 2010 Microchip Technology Inc. Data Sheet 64/80/100-Pin, 16-Bit, with Peripheral Pin Select DS39905E ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Microchip Technology Inc. PIC24FJ256GA110 FAMILY Peripheral Features: • Peripheral Pin Select: - Allows independent I/O mapping of many peripherals at run time - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes - available pins (100-pin devices) • ...
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... Selectable write protection boundary - Write protection option for Flash Configuration Words ( PIC24FJ64GA106 43 PIC24FJ128GA106 42 41 PIC24FJ192GA106 40 PIC24FJ256GA106 SOSCO/C3INC/RPI37/T1CK/CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/CN49/RD0 RP12/CN56/PMCS1/RD11 RP3/CN55/PMCS2/RD10 RP4/CN54/RD9 RTCC/RP2/CN53/RD8 V SS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 V DD SCL1/CN83/RG2 SDA1/CN84/RG3 ASCK1/RPI45/INT0/CN72/RF6 RP30/CN70/RF2 RP16/CN71/RF3 . SS 2010 Microchip Technology Inc. ...
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... MCLR 9 C2INC/RP27/CN11/PMA2/RG9 TMS/RPI33/CN66/RE8 13 TDO/RPI34/CN67/RE9 14 PGEC3/AN5/C1INA/CN7/RP18/RB5 15 PGED3/AN4/C1INB/RP28/CN6/RB4 16 AN3/C2INA/CN5/RB3 17 AN2/C2INB/RP13/CN4/RB2 18 PGEC1/AN1/RP1/CN3/RB1 19 PGED1/AN0/RP0/CN2/RB0 20 Shaded pins indicate pins tolerant +5.5 V Legend: RPn represents remappable pins for Peripheral Pin Select (PPS) feature. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY PIC24FJ64GA108 53 PIC24FJ128GA108 52 51 PIC24FJ192GA108 50 PIC24FJ256GA108 SOSCO/C3INC/ RPI37/T1CK/CN0/RC14 ...
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... RPn represents remappable pins for Peripheral Pin Select (PPS) feature. DS39905E-page PIC24FJ64GA110 66 65 PIC24FJ128GA110 64 PIC24FJ192GA110 63 62 PIC24FJ256GA110 2010 Microchip Technology Inc SOSCO/C3INC/ RPI37/T1CK/CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/CN49/RD0 RP12/CN56/PMCS1/RD11 RP3/CN55/PMCS2/RD10 RP4/CN54/RD9 RTCC/RP2/CN53/RD8 ASDA2/RPI35/CN44/RA15 ASCL2/RPI36/CN43/RA14 V SS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 V DD TDO/CN38/RA5 TDI/CN37/RA4 SDA2/CN36/RA3 SCL2/CN35/RA2 SCL1/CN83/RG2 SDA1/CN84/RG3 ASCK1/RPI45/INT0/CN72/RF6 RPI44/CN73/RF7 RP15/CN74/RF8 RP30/CN70/RF2 RP16/CN71/RF3 ...
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... Electrical Characteristics .......................................................................................................................................................... 269 29.0 Packaging Information.............................................................................................................................................................. 305 Appendix A: Revision History............................................................................................................................................................. 319 Index ................................................................................................................................................................................................. 321 The Microchip Web Site ..................................................................................................................................................................... 327 Customer Change Notification Service .............................................................................................................................................. 327 Customer Support .............................................................................................................................................................................. 327 Reader Response .............................................................................................................................................................................. 328 Product Identification System ............................................................................................................................................................ 329 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY DS39905E-page 7 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39905E-page 8 2010 Microchip Technology Inc. ...
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... Timer1 source or the internal, low-power RC Oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, ...
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... Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Figure 1-1. memory (64 Kbytes for Table 1-1. the pin features available on the 1-4. Note that this table shows the pin 2010 Microchip Technology Inc. ...
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... CTMU Interface Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Instruction Set Packages Peripherals are accessible through remappable pins. Note 1: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY PIC24FJ128GA106 PIC24FJ192GA106 PIC24FJ256GA106 DC – 32 MHz 64K 128K 22,016 44,032 ...
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... Yes Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 80-Pin TQFP 192K 256K 67,072 87,552 2010 Microchip Technology Inc. ...
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... JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) Instruction Set Packages Peripherals are accessible through remappable pins. Note 1: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY DC – 32 MHz 64K 128K 22,016 44,032 16,384 66 (62/4) Ports ...
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... ADC SPI UART I2C (3) 1/2/3 1/2/3 (3) 1/2/3/4 Table 1-4 (1) PORTA 16 (13 I/O) PORTB Latch (16 I/ (1) PORTC (8 I/ (1) PORTD (16 I/O) (1) PORTE (10 I/O) PORTF (1) 16-Bit ALU (11 I/O) 16 (1) PORTG (12 I/O) Comparators (3) PMP/PSP CTMU for specific implementations by pin count. 2010 Microchip Technology Inc. ...
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... C3INB 54 68 C3INC 48 60 C3IND 47 59 CLKI 39 49 CLKO 40 50 TTL = TTL input buffer Legend: ANA = Analog level input/output 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Input I/O 100-Pin Buffer TQFP 25 I ANA A/D Analog Inputs ANA 23 I ANA 22 I ANA ...
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... CN39 — — CN40 — — CN41 — 23 CN42 — 24 TTL = TTL input buffer Legend: ANA = Analog level input/output DS39905E-page 16 Input I/O Buffer TQFP Interrupt-on-Change Inputs Schmitt Trigger input buffer C™ C/SMBus input buffer Description 2010 Microchip Technology Inc. ...
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... CN78 — 74 CN79 — — CN80 — — CN81 — — CN82 — — CN83 37 47 CN84 36 46 TTL = TTL input buffer Legend: ANA = Analog level input/output 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Input I/O 100-Pin Buffer TQFP Interrupt-on-Change Inputs ...
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... ST/TTL 98 I/O ST/TTL 99 I/O ST/TTL 100 I/O ST/TTL 3 I/O ST/TTL 4 I/O ST/TTL 5 I/O ST/TTL 82 O — Parallel Master Port Read Strobe — Parallel Master Port Write Strobe Schmitt Trigger input buffer C™ C/SMBus input buffer Description 2010 Microchip Technology Inc. ...
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... RC3 — 5 RC4 — — RC12 39 49 RC13 47 59 RC14 48 60 RC15 40 50 TTL = TTL input buffer Legend: ANA = Analog level input/output 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Input I/O 100-Pin Buffer TQFP 17 I/O ST PORTA Digital I/ I/O ...
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... I/O ST PORTE Digital I/ I/O ST 100 — Reference Clock Output. 87 I/O ST PORTF Digital I/ Schmitt Trigger input buffer C™ C/SMBus input buffer Description 2010 Microchip Technology Inc. ...
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... RP26 5 7 RP27 8 10 RP28 12 16 RP29 30 36 RP30 34 42 RP31 — — TTL = TTL input buffer Legend: ANA = Analog level input/output 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Input I/O 100-Pin Buffer TQFP 90 I/O ST PORTG Digital I/ I/O ...
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... Positive Supply for Microcontroller Core Logic (regulator disabled ANA A/D and Comparator Reference Voltage (low) Input ANA A/D and Comparator Reference Voltage (high) Input. P — Ground Reference for Logic and I/O Pins. 65 Schmitt Trigger input buffer C™ C/SMBus input buffer Description 2010 Microchip Technology Inc. ...
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... REF REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY FIGURE 2- MCLR ( Pin” ...
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... The DD may be beneficial. A typical Figure 2-1. Other circuit ) and fast signal transitions must IL (Figure 2-2). is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC24FXXXX JP C1 and V specifications are met and V specifications are met. IL 2010 Microchip Technology Inc. ...
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... C3216X7R1C106K TDK C3216X5R1C106K Panasonic ECJ-3YX1C106K Panasonic ECJ-4YB1C106K Murata GRM32DR71C106KA01L Murata GRM31CR61C106KC31L 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Designers may use equivalence of candidate devices. The placement of this capacitor should be close CAP DDCORE length not exceed 0.25 inch (6 mm). Refer to Section 28.0 additional information ...
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... Channel Select” (i.e., PGECx/PGEDx programmed into the device, matches the physical connections for the ICSP to debugger/emulator tool. For more information on available development tools connection requirements, refer to Section 27.0 “Development Support”. 2010 Microchip Technology Inc pins), the Microchip Microchip ...
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... AN849, “Basic PICmicro Oscillator Design” ® • AN943, “Practical PICmicro Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY FIGURE 2-5: (refer to Single-Sided and In-line Layouts: for details). Copper Pour ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor to V output to logic low. on unused pins and drive the SS 2010 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... Decode & Control Control Signals to Various Blocks DS39905E-page 30 Data Bus Data Latch PCL Data RAM Address Loop Latch Control Logic 16 RAGU WAGU EA MUX ROM Latch 16 Instruction Reg Hardware Multiplier Register Array Divide Support 16-Bit ALU Peripheral Modules 2010 Microchip Technology Inc. ...
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... W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register ...
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... Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39905E-page 32 U-0 U-0 — — (1) R-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,2) U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown 2010 Microchip Technology Inc. ...
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... PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ User interrupts are disabled when IPL3 = 1. Note 1: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 3-2. Description 2010 Microchip Technology Inc. ...
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... Device Config Registers Device Config Registers Reserved DEVID (2) Memory areas are not shown to scale. Note: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Program and Data Memory ...
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... Section 25.1 Bits”. FLASH CONFIGURATION WORDS FOR PIC24FJ256GA110 FAMILY DEVICES Program Configuration Memory Word (Words) Addresses 00ABFEh: 22,016 00AC00h 0157FAh: 44,032 0157FEh 020BFAh: 67,072 020BFEh 02ABFAh: 87,552 02ABFEh PC Address (lsw Address) 0 000000h 000002h 000004h 000006h 2010 Microchip Technology Inc. ...
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... FFFFh Data memory areas are not shown to scale. Note: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY PIC24FJ256GA110 family devices implement a total of 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. ...
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... CRC — System NVM/PMD — 4-2. Each implemented area indicates 4-3 through 4-29. xxA0 xxC0 xxE0 Interrupts — Compare UART I/O — — — — — — — PPS — — — — 2010 Microchip Technology Inc. ...
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TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
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TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNPD1 0054 CN15PDE CN14PDE CN13PDE CN12PDE CN11PDE CNPD2 0056 CN31PDE CN30PDE CN29PDE CN28PDE CN27PDE (1) (2) (1) (1) CNPD3 0058 CN47PDE CN46PDE CN45PDE CN44PDE ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...
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TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...
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TABLE 4-7: INPUT CAPTURE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 IC1CON2 0142 — — — — IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 — — ICSIDL ICTSEL2 ...
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TABLE 4-8: OUTPUT COMPARE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A — ...
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TABLE 4-8: OUTPUT COMPARE REGISTER MAP (CONTINUED) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name OC8CON1 01D6 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN OCINV OC8RS 01DA OC8R 01DC OC8TMR 01DE OC9CON1 01E0 ...
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TABLE 4-10: UART REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — — ...
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TABLE 4-12: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 TRISA15 TRISA14 — — PORTA 02C2 RA15 RA14 — — LATA 02C4 LATA15 LATA14 — — ODCA 02C6 ODA15 ODA14 — ...
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TABLE 4-16: PORTE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISE 02E0 — — — — PORTE 02E2 — — — — LATE 02E4 — — — — ODCE 02E6 — — — — ...
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TABLE 4-20: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
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TABLE 4-22: PARALLEL MASTER/SLAVE PORT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 PMADDR 0604 CS2 CS1 ADDR13 ADDR12 ...
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TABLE 4-26: PERIPHERAL PIN SELECT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — INT1R5 INT1R4 RPINR1 0682 — — INT3R5 INT3R4 RPINR2 0684 — — — — RPINR3 0686 — — ...
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TABLE 4-27: SYSTEM REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 — — — — ...
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... W15 (before CALL) PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... Bits 24 Bits Select 1 PSVPAG 0 8 Bits 23 Bits <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 Bits Bits Byte Select 2010 Microchip Technology Inc. ...
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... FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...
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... PSV Area 800000h 1111’ or 0000h Data EA<14:0> 8000h ...while the lower 15 bits of the EA specify an exact address within the FFFFh PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 2010 Microchip Technology Inc. ...
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... Using Table Instruction User/Configuration Space Select 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- tions (192 bytes time and erase program memory in blocks of 512 instructions (1536 bytes time ...
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... Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the opera- tion and the WR bit is automatically cleared when the operation is finished. 2010 Microchip Technology Inc. ...
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... Memory row program operation (ERASE = operation (ERASE = 1) These bits can only be reset on POR. Note 1: All other combinations of NVMOP<3:0> are unimplemented. 2: Available in ICSP™ mode only. Refer to the device programming specification. 3: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY (1) U-0 U-0 — — ...
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... Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted functions, is shown in 5-4 and 5-6. 2010 Microchip Technology Inc. ...
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... MOV #LOW_WORD_31, W2 MOV #HIGH_BYTE_31, W3 TBLWTL W2, [W0] TBLWTH W3, [W0] 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY // Address of row to write // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts with priority <7 ...
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... Initialize lower word of address // Write to address low word // Write to upper byte // Increment address ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; ; ; and wait for completed 2010 Microchip Technology Inc. ...
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... TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); __builtin_tblwth(offset, progDataH); asm(“DISI #5”); __builtin_write_NVM(); 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to ‘ ...
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... PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 64 2010 Microchip Technology Inc. ...
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... Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...
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... SWDTEN bit setting. DS39905E-page 66 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 R/W-0 R/W-0 — CM PMSLP bit 8 R/W-1 R/W-1 IDLE BOR POR bit Bit is unknown 2010 Microchip Technology Inc. ...
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... POR FNOSC Configuration bits (CW2<10:8>) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Setting Event 6.2 Device Reset Times The Reset times for various types of device Reset are 6-2. If clock summarized in Table signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... POR PWRT RST OST LOCK — PWRT RST PWRT RST FRC PWRT RST LPRC PWRT RST LOCK PWRT RST FRC LOCK PWRT RST OST PWRT RST FRC LOCK T — RST ). SS Section 28.0 “Electrical 2010 Microchip Technology Inc. Notes Characteristics”. ...
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... FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR). 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 6.3 Special Function Register Reset ...
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... PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 70 2010 Microchip Technology Inc. ...
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... PIC24FJ256GA110 family devices non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in AIVT is provided (INTCON2< ...
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... Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 000112h Reserved (1) (1) Trap Source 2010 Microchip Technology Inc. ...
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... Output Compare 6 Output Compare 7 Output Compare 8 Output Compare 9 Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Vector AIVT IVT Address Address 13 00002Eh 00012Eh 18 000038h 000138h ...
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... IEC4<1> IPC16<6:4> IEC0<11> IPC2<14:12> IEC0<12> IPC3<2:0> IEC4<2> IPC16<10:8> IEC1<14> IPC7<10:8> IEC1<15> IPC7<14:12> IEC5<1> IPC20<6:4> IEC5<2> IPC20<10:8> IEC5<3> IPC20<14:12> IEC5<7> IPC21<14:12> IEC5<8> IPC22<2:0> IEC5<9> IPC22<6:4> 7-2. For example, the INT0 (External Register 7-1 7-38, on the following pages. 2010 Microchip Technology Inc. ...
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... Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control Note 1: functions. The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. 2: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 — — ...
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... Unimplemented: Read as ‘0’ DS39905E-page 76 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown 2010 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — ...
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... Interrupt request has not occurred DS39905E-page 78 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF1IF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown 2010 Microchip Technology Inc. ...
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... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF ...
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... Interrupt request has not occurred DS39905E-page 80 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPF2IF bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — ...
Page 82
... Unimplemented: Read as ‘0’ DS39905E-page 82 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2010 Microchip Technology Inc. U-0 R/W-0 — LVDIF bit 8 R/W-0 U-0 U1ERIF — bit Bit is unknown ...
Page 83
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 OC9IF SPI3IF SPF3IF ...
Page 84
... Interrupt request not enabled DS39905E-page 84 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF1IE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 85
... Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn Note 1: pin. See Section 10.4 “Peripheral Pin Select” 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 (1) T5IE T4IE ...
Page 86
... SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn Note 1: pin. See Section 10.4 “Peripheral Pin Select” DS39905E-page 86 for more information. 2010 Microchip Technology Inc. ...
Page 87
... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE ...
Page 88
... U-0 — — U-0 U-0 (1) — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) for more information. U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 SI2C2IE — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 89
... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 90
... Unimplemented: Read as ‘0’ DS39905E-page 90 R/W-0 R/W-0 R/W-0 OC9IE SPI3IE SPF3IE R/W-0 R/W-0 R/W-0 SI2C3IE U3TXIE U3RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U4TXIE U4RXIE bit 8 R/W-0 U-0 U3ERIE — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 91
... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 ...
Page 92
... Unimplemented: Read as ‘0’ DS39905E-page 92 R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC2IP1 OC2IP0 bit 8 U-0 U-0 — — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 ...
Page 94
... Interrupt source is disabled DS39905E-page 94 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — U1TXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 U1TXIP1 U1TXIP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 95
... Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 ...
Page 96
... Interrupt source is disabled DS39905E-page 96 R/W-0 U-0 R/W-1 IC8IP0 — IC7IP2 U-0 U-0 R/W-1 — — INT1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC7IP1 IC7IP0 bit 8 R/W-0 R/W-0 INT1IP1 INT1IP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 97
... OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 ...
Page 98
... Interrupt source is disabled DS39905E-page 98 R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — T5IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2RXIP1 U2RXIP0 bit 8 R/W-0 R/W-0 T5IP1 T5IP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 99
... Unimplemented: Read as ‘0’ bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 100
... Unimplemented: Read as ‘0’ DS39905E-page 100 R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC4IP1 IC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 101
... Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 R/W-1 OC7IP0 — OC6IP2 R/W-0 ...
Page 102
... Interrupt source is disabled DS39905E-page 102 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 PMPIP0 — OC8IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 OC8IP1 OC8IP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 103
... SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 R/W-1 — — MI2C2IP2 R/W-0 ...
Page 104
... Unimplemented: Read as ‘0’ DS39905E-page 104 U-0 U-0 R/W-1 — — INT4IP2 R/W-0 U-0 U-0 INT3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 INT4IP1 INT4IP0 bit 8 U-0 U-0 — — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 105
... RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 ...
Page 106
... Unimplemented: Read as ‘0’ DS39905E-page 106 R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2ERIP1 U2ERIP0 bit 8 U-0 U-0 — — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 107
... CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 108
... Unimplemented: Read as ‘0’ DS39905E-page 108 R/W-0 U-0 R/W-1 U3TXIP0 — U3RXIP2 R/W-0 U-0 U-0 U3ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U3RXIP1 U3RXIP0 bit 8 U-0 U-0 — — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 109
... Unimplemented: Read as ‘0’ bit 2-0 SI2C3IP<2:0>: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 R/W-0 U4ERIP0 — — R/W-0 ...
Page 110
... Interrupt source is disabled DS39905E-page 110 R/W-0 U-0 R/W-1 SPI3IP0 — SPF3IP2 R/W-0 U-0 R/W-1 U4TXIP0 — U4RXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF3IP1 SPF3IP0 bit 8 R/W-0 R/W-0 U4RXIP1 U4RXIP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 111
... Unimplemented: Read as ‘0’ bit 2-0 OC9IP<2:0>: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 112
... Interrupt vector pending is number 8 DS39905E-page 112 U-0 R-0 R-0 — ILR3 ILR2 R-0 R-0 R-0 VECNUM4 VECNUM3 VECNUM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 ILR1 ILR0 bit 8 R-0 R-0 VECNUM1 VECNUM0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 113
... ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 114
... PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 114 2010 Microchip Technology Inc. ...
Page 115
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects ...
Page 116
... Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 Section 25.1 “Configu- for further details). The Primary bits, POSCMD<1:0> bits, FNOSC<2:0> Table 8-1. Configuration bits (Configuration FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000 2010 Microchip Technology Inc. ...
Page 117
... IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. Also, resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 3: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY The CLKDIV register features associated with Doze mode, as well as the postscaler for the FRC Oscillator ...
Page 118
... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. Also, resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 3: DS39905E-page 118 (2) (3) 2010 Microchip Technology Inc. ...
Page 119
... MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) bit 7-0 Unimplemented: Read as ‘0’ This bit is automatically cleared when the ROI bit is set and an interrupt occurs. Note 1: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 ...
Page 120
... The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled held at ‘0’ at all times. U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown for further details.) 2010 Microchip Technology Inc. ...
Page 121
... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence ...
Page 122
... POSCEN bit is also not set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the refer- ence output frequency to change as the system clock changes during any clock switches. 2010 Microchip Technology Inc. ...
Page 123
... Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 ...
Page 124
... PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 124 2010 Microchip Technology Inc. ...
Page 125
... Put the device into SLEEP mode PWRSAV #1 ; Put the device into IDLE mode 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes said to “ ...
Page 126
... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows possible further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications. 2010 Microchip Technology Inc. ...
Page 127
... CK WR PORT Data Latch Read LAT Read PORT 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 128
... PORTE<9:0> PORTF<13:12>, PORTF<8:1> PORTG<15:12>, PORTG<3:0> Not all port pins shown here are imple- Note 1: mented on 64-pin and 80-pin devices. Refer to Section 1.0 “Device Overview” to confirm which ports are available in specific devices. 2010 Microchip Technology Inc. (1) Description input DD , useful for ...
Page 129
... Pull-ups on change notification pins Note: should always be disabled whenever the port pin is configured as a digital output. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 10.4 Peripheral Pin Select A major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins ...
Page 130
... Additionally, no other RPOUT register should be configured to output the SCK1OUT function while SCK1CM is set Register 10-1 10-21). Each register contains two Register 10-22 10-37). The value of the bit field cor- Table 10-3). 2010 Microchip Technology Inc. ...
Page 131
... UART2 Clear To Send UART2 Receive UART3 Clear To Send UART3 Receive UART4 Clear To Send UART4 Receive Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. Note 1: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Register INT1 RPINR0 INT2 RPINR1 INT3 RPINR1 ...
Page 132
... UART3 Request To Send U4TX UART4 Transmit (3) U4RTS UART4 Request To Send SDO3 SPI3 Data Output SCK3OUT SPI3 Clock Output SS3OUT SPI3 Slave Select Output OC9 Output Compare 9 C3OUT Comparator 3 Output (unused) for more information. 2010 Microchip Technology Inc. Output Name Null NC ...
Page 133
... Total 64-pin 29 80-pin 31 100-pin 32 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 10.4.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these reg- isters, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON< ...
Page 134
... Configure Input Functions (Table 9-1)) // Assign U1RX To Pin RP0 RPINR18bits.U1RXR = 0; // Assign U1CTS To Pin RP1 RPINR18bits.U1CTSR = 1; // Configure Output Functions (Table 9-2) // Assign U1TX To Pin RP2 RPOR1bits.RP2R = 3; // Assign U1RTS To Pin RP3 RPOR1bits.RP3R = 4; // Lock Registers __builtin_write_OSCCONL(OSCCON | 0x40); CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS 2010 Microchip Technology Inc. ...
Page 135
... INT3R<5:0>: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Input and output register values can only Note: be changed if IOLOCK (OSCCON<6> ...
Page 136
... T2CKR4 T2CKR3 T2CKR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-1 R/W-1 INT4R1 INT4R0 bit Bit is unknown R/W-1 R/W-1 T3CKR1 T3CKR0 bit 8 R/W-1 R/W-1 T2CKR1 T2CKR0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 137
... IC2R<5:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-1 R/W-1 R/W-1 T5CKR4 ...
Page 138
... IC5R4 IC5R3 IC5R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC4R1 IC4R0 bit 8 R/W-1 R/W-1 IC3R1 IC3R0 bit Bit is unknown R/W-1 R/W-1 IC6R1 IC6R0 bit 8 R/W-1 R/W-1 IC5R1 IC5R0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 139
... OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-1 R/W-1 R/W-1 IC8R4 ...
Page 140
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC9R1 IC9R0 bit 8 U-0 U-0 — — bit Bit is unknown R/W-1 R/W-1 U3RXR1 U3RXR0 bit 8 U-0 U-0 — — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 141
... U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR<5:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-1 R/W-1 R/W-1 U1CTSR4 ...
Page 142
... SS1R4 SS1R3 SS1R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 SCK1R1 SCK1R0 bit 8 R/W-1 R/W-1 SDI1R1 SDI1R0 bit Bit is unknown R/W-1 R/W-1 U3CTSR1 U3CTSR0 bit 8 R/W-1 R/W-1 SS1R1 SS1R0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 143
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 ...
Page 144
... SDI3R4 SDI3R3 SDI3R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 U4CTSR1 U4CTSR0 bit 8 R/W-1 R/W-1 U4RXR1 U4RXR0 bit Bit is unknown R/W-1 R/W-1 SCK3R1 SCK3R0 bit 8 R/W-1 R/W-1 SDI3R1 SDI3R0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 145
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS3R<5:0>: Assign SPI3 Slave Select Input (SS31IN) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 U-0 — — — ...
Page 146
... Table 10-3 for peripheral function numbers). Table 10-3 for peripheral function numbers). R/W-0 R/W-0 RP1R1 RP1R0 bit 8 R/W-0 R/W-0 RP0R1 RP0R0 bit Bit is unknown R/W-0 R/W-0 RP3R1 RP3R0 bit 8 R/W-0 R/W-0 RP2R1 RP2R0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 147
... RP7R<5:0>: RP7 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP7 (see bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP6R<5:0>: RP6 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP6 (see 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 (1) (1) (1) ...
Page 148
... Table 10-3 for peripheral function numbers). Table 10-3 for peripheral function numbers). R/W-0 R/W-0 RP9R1 RP9R0 bit 8 R/W-0 R/W-0 RP8R1 RP8R0 bit Bit is unknown R/W-0 R/W-0 RP11R1 RP11R0 bit 8 R/W-0 R/W-0 RP10R1 RP10R0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 149
... Unimplemented: Read as ‘0’ bit 5-0 RP14R<5:0>: RP14 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP14 (see Unimplemented in 64-pin devices; read as ‘0’. Note 1: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 RP13R4 RP13R3 ...
Page 150
... Table 10-3 for peripheral function numbers). Table 10-3 for peripheral function numbers). R/W-0 R/W-0 RP17R1 RP17R0 bit 8 R/W-0 R/W-0 RP16R1 RP16R0 bit Bit is unknown R/W-0 R/W-0 RP19R1 RP19R0 bit 8 R/W-0 R/W-0 RP18R1 RP18R0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 151
... Peripheral output number n is assigned to pin, RP23 (see bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP22R<5:0>: RP22 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP22 (see 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 ...
Page 152
... Table 10-3 for peripheral function numbers). Table 10-3 for peripheral function numbers). R/W-0 R/W-0 RP25R1 RP25R0 bit 8 R/W-0 R/W-0 RP24R1 RP24R0 bit Bit is unknown R/W-0 R/W-0 RP27R1 RP27R0 bit 8 R/W-0 R/W-0 RP26R1 RP26R0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 153
... Unimplemented: Read as ‘0’ bit 5-0 RP30R<5:0>: RP30 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP30 (see Unimplemented in 64-pin and 80-pin devices; read as ‘0’. Note 1: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 R/W-0 RP29R4 RP29R3 ...
Page 154
... SCK1 output function is mapped according to RPORn registers DS39905E-page 154 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2010 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 R/W-0 — SCK1CM bit Bit is unknown ...
Page 155
... TIMER1 MODULE BLOCK DIAGRAM SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS< ...
Page 156
... DS39905E-page 156 (1) U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 157
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). ...
Page 158
... The ADC event trigger is available only on Timer2/3 in 32-bit mode and Timer3 in 16-bit mode. 3: DS39905E-page 158 1x Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR2 TMR3 (TMR4) (TMR5 TMR3HLD (TMR5HLD) TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 (2) TGATE (2) TCS Sync 2010 Microchip Technology Inc. ...
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... Equal The Timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Note 1: Pin Select” for more information. The ADC event trigger is available only on Timer3. 2: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 1x Gate Sync 01 ...
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... DS39905E-page 160 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /2) (3) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (2) — TCS — bit Bit is unknown 2010 Microchip Technology Inc. ...
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... If TCS = 1, RPINRx (TyCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral 2: Pin Select” for more information. Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to 3: reset and is not recommended. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY U-0 U-0 (1) — ...
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... PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 162 2010 Microchip Technology Inc. ...
Page 163
... Reset Trigger and Sync Sources Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see for more information. Pin Select” 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 13.1 General Operating Modes 13.1.1 SYNCHRONOUS AND TRIGGER MODES By default, the enhanced input capture module oper- ates in a free-running mode ...
Page 164
... ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (perform automatically by hardware). 2010 Microchip Technology Inc. modules Trigger or ...
Page 165
... Input capture module turned off The ICx input must also be configured to an available RPn pin. For more information, see Note 1: “Peripheral Pin Select”. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 R/W-0 ICTSEL2 ICTSEL1 ...
Page 166
... DS39905E-page 166 U-0 U-0 — — R/W-0 R/W-1 SYNCSEL4 SYNCSEL3 SYNCSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) U-0 U-0 R/W-0 — — IC32 bit 8 R/W-1 R/W-0 R/W-1 SYNCSEL1 SYNCSEL0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 167
... Compare or PWM events are generated each time a match between the internal counter and one of the Period registers occurs. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module’ ...
Page 168
... OCxR Match Event Comparator OCxTMR Reset Match Event Comparator OCxRS the time base source with the OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 (1) OCx Pin OC Output and Fault Logic OCFA/OCFB OCx Interrupt Section 10.4 “Peripheral 2010 Microchip Technology Inc. ...
Page 169
... Single Compare modes, and after each OCxRS match in Double Compare modes. Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuous pulse events continue indefinitely until terminated. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 14.3 Pulse-Width Modulation (PWM) Mode registers ...
Page 170
... MIPS and 10 MIPS, respectively. OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 OCx Pin OC Output and (1) Fault Logic OCFA/OCFB OCx Interrupt Section 10.4 “Peripheral for PWM mode timing details. Table 14-2 show example PWM 2010 Microchip Technology Inc. ...
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... PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Based /2, Doze mode and PLL are disabled. Note 1: CY OSC 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY ( F CY log 10 F • (Timer Prescale Value) PWM log ( /2, Doze mode and PLL are disabled. ...
Page 172
... OCTSEL2 OCTSEL1 OCTSEL0 R/W-0, HCS R/W-0 R/W-0 OCFLT0 TRIGMODE OCM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) CY (1) (2) (2) U-0 U-0 — — bit 8 R/W-0 R/W-0 (1) (1) (1) OCM1 OCM0 bit Bit is unknown Section 10.4 2010 Microchip Technology Inc. ...
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... Output Compare Peripheral x connected to the OCx pin Never use an OC module as its own trigger source, either by selecting this mode or another equivalent Note 1: SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources. 2: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY R/W-0 U-0 U-0 OCINV — ...
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... Never use an OC module as its own trigger source, either by selecting this mode or another equivalent Note 1: SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources. 2: DS39905E-page 174 (1) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (1) (1) (1) (1) (1) (1) (1) (1) (1) 2010 Microchip Technology Inc. ...
Page 175
... Enhanced Buffer mode. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY The SPI serial interface consists of four pins: • SDIx: Serial Data Input • ...
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... Clear the SPIROV bit (SPIxSTAT<6>). 7. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPIxBUF 16 Internal Data Bus 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock 2010 Microchip Technology Inc. ...
Page 177
... SDOx bit0 SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: a) Clear the SPIxIF bit in the respective IFSx register ...
Page 178
... SPIBEC2 R/W-0 R/W-0 SISEL2 SISEL1 HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) for more information. R-0 R-0 R-0 SPIBEC1 SPIBEC0 bit 8 R/W-0 R-0 R-0 SISEL0 SPITBF SPIRBF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 179
... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. If SPIEN = 1, these functions must be assigned to available RPn pins (or to ASCK1 for the SCK1 output) Note 1: before use. See Section 10.4 “Peripheral Pin Select” 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY for more information. DS39905E-page 179 ...
Page 180
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) for more information. Section 10.4 “Peripheral Pin Section 10.4 “Peripheral Pin Select” R/W-0 R/W-0 (3) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 181
... Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY for more information. Section 10.4 “Peripheral Pin Section 10.4 “Peripheral Pin Select” ...
Page 182
... SDIx SDIx SDOx Serial Clock SCKx SCKx SSx (1) SSx SSEN (SPIxCON1<7> MSTEN (SPIxCON1<5> and SPIBEN (SPIxCON2<0> (SPIxRXB) Shift Register (SPIxSR) LSb (SPIxTXB) SPIx Buffer (2) (SPIxBUF) Shift Register (SPIxSR) MSb LSb 8-Level FIFO Buffer SPIx Buffer (2) (SPIxBUF) 2010 Microchip Technology Inc. ...
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... FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Master) FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx ...
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... Microchip Technology Inc. ...
Page 185
... ASCL2 and ASDA2 during device configuration. Pin assignment is controlled by the I2C2SEL Configu- ration bit; programming this bit (= 0) multiplexes the module to the ASCL2 and ASDA2 pins. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 16.2 Communicating as a Master in a Single Master Environment ...
Page 186
... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read 2010 Microchip Technology Inc. ...
Page 187
... Note 1: The address will be Acknowledged only if GCEN = 1. 2: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. 3: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 16.4 Slave Address Masking The I2CxMSK register address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
Page 188
... R/W-0, HC R/W-0, HC R/W-0, HC ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C pins are controlled by port functions Slave slave slave) R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Repeated Start condition not in progress bit 0 SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 2 C master. Applicable during master receive master ...
Page 190
... HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C slave) R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit 0 HSC = Hardware Settable/Clearable bit x = Bit is unknown 2 C module is busy 2010 Microchip Technology Inc. ...
Page 191
... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 2 C slave device address byte. ...
Page 192
... Disable masking for bit x; bit match required in this position DS39905E-page 192 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 AMSK4 AMSK3 AMSK2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 193
... UARTx Transmitter The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Note: Section 10.4 “Peripheral Pin Select” 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • ...
Page 194
... UART BAUD RATE WITH (1,2) BRGH = • (UxBRG + – • Baud Rate denotes the instruction cycle clock = F /2, Doze mode CY OSC /4 CY (1) 2010 Microchip Technology Inc. ...
Page 195
... Write ‘55h’ to UxTXREG; this loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY 17.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
Page 196
... RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) for more information. R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 197
... One Stop bit If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Note 1: Section 10.4 “Peripheral Pin Select” This feature is only available for the 16x BRG mode (BRGH = 0). 2: 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY /4) CY /16) CY for more information ...
Page 198
... R-0 RIDLE PERR FERR HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) for more information. R-0 R-1 (2) UTXBF TRMT bit 8 R/C-0 R-0 OERR URXDA bit Bit is unknown ® encoder is enabled (IREN = 1). 2010 Microchip Technology Inc. ...
Page 199
... Value of bit only affects the transmit properties of the module when the IrDA Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See 2: Section 10.4 “Peripheral Pin Select” 2010 Microchip Technology Inc. PIC24FJ256GA110 FAMILY ® for more information. encoder is enabled (IREN = 1). ...
Page 200
... PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 200 2010 Microchip Technology Inc. ...