PIC24FJ64GA106T-I/PT Microchip Technology, PIC24FJ64GA106T-I/PT Datasheet - Page 116

• Manufacturer Part Number: PIC24FJ64GA106T-I/PT
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA106T-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GA110 FAMILY
8.1
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
• Secondary Oscillator (SOSC) on the SOSCI and
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The Primary Oscillator and FRC sources have the
option of using the internal 4x PLL. The frequency of
the FRC clock source can optionally be reduced by the
programmable clock divider. The selected clock source
generates the processor and peripheral clock sources.
The processor clock source is divided by two to pro-
duce the internal instruction cycle clock, F
document, the instruction cycle clock is also denoted
by F
can be provided on the OSCO I/O pin for some
operating modes of the Primary Oscillator.
TABLE 8-1:
DS39905E-page 116
Fast RC Oscillator with Postscaler
(FRCDIV)
(Reserved)
Low-Power RC Oscillator (LPRC)
Secondary (Timer1) Oscillator
(SOSC)
Primary Oscillator (XT) with PLL
Module (XTPLL)
Primary Oscillator (EC) with PLL
Module (ECPLL)
Primary Oscillator (HS)
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL Module
(FRCPLL)
Fast RC Oscillator (FRC)
Note 1:
OSCO pins
SOSCO pins
OSC
2:
/2. The internal instruction cycle clock, F
CPU Clocking Scheme
Oscillator Mode
OSCO pin function is determined by the OSCIOFCN Configuration bit.
This is the default oscillator mode for an unprogrammed (erased) device.
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Source
CY
Secondary
Primary
Primary
Primary
Primary
Primary
. In this
Internal
Internal
Internal
Internal
Internal
OSC
/2,
8.2
The oscillator source (and operating mode) that is used
at a device Power-on Reset event is selected using
Configuration bit settings. The oscillator Configuration
bit settings are located in the Configuration registers in
the program memory (refer to
ration Bits”
Oscillator
(Configuration Word 2<1:0>), and the Initial Oscillator
Select
(Configuration Word 2<10:8>), select the oscillator
source that is used at a Power-on Reset. The FRC
Primary Oscillator with Postscaler (FRCDIV) is the
default (unprogrammed) selection. The Secondary
Oscillator, or one of the internal oscillators, may be
chosen by programming these bit locations.
The Configuration bits allow users to choose between
the various clock modes, shown in
8.2.1
The
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when
FCKSM<1:0> are both programmed (‘00’).
POSCMD<1:0>
FCKSM
11
xx
11
11
01
00
10
01
00
11
11
Initial Configuration on POR
Configuration
CLOCK SWITCHING MODE
CONFIGURATION BITS
Configuration
for further details). The Primary
Configuration
 2010 Microchip Technology Inc.
FNOSC<2:0>
111
110
101
100
011
011
010
010
010
001
000
Section 25.1 “Configu-
bits,
bits,
bits
Table
POSCMD<1:0>
FNOSC<2:0>
(Configuration
8-1.
Note
1, 2
1
1
1
1
1