PIC24FJ64GA106T-I/PT Microchip Technology, PIC24FJ64GA106T-I/PT Datasheet - Page 128

• Manufacturer Part Number: PIC24FJ64GA106T-I/PT
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA106T-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GA110 FAMILY
10.1.1
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually con-
figured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than V
digital only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
10.2
The AD1PCFGL and TRIS registers control the opera-
tion of the A/D port pins. Setting a port pin as an analog
input also requires that the corresponding TRIS bit be
set. If the TRIS bit is cleared (output), the digital output
level (V
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
10.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
EXAMPLE 10-1:
DS39905E-page 128
MOV
MOV
NOP
BTSS
OH
0xFF00, W0
W0, TRISB
PORTB, #13
Configuring Analog Port Pins
or V
OPEN-DRAIN CONFIGURATION
I/O PORT WRITE/READ TIMING
OL
IH
) will be converted.
specification.
PORT WRITE/READ EXAMPLE
DD
(e.g., 5V) on any desired
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
10.2.2
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to V
beyond V
Table 10-1
Section 28.1 “DC Characteristics”
TABLE 10-1:
PORTA<10:9>
PORTB<15:0>
PORTC<15:12>
PORTD<7:6>
PORTF<0>
PORTG<9:6>
PORTA<15:14>,
PORTA<7:0>
PORTC<4:1>
PORTD<15:8>,
PORTD<5:0>
PORTE<9:0>
PORTF<13:12>,
PORTF<8:1>
PORTG<15:12>,
PORTG<3:0>
Note 1:
Note:
Port or Pin
DD
summarizes the input capabilities. Refer to
Not all port pins shown here are imple-
mented on 64-pin and 80-pin devices.
Refer to
to confirm which ports are available in
specific devices.
ANALOG INPUT PINS AND
VOLTAGE CONSIDERATIONS
For easy identification, the pin diagrams at
the beginning of this data sheet also
indicate 5.5V tolerant pins with dark grey
shading.
on these pins are always to be avoided.
INPUT VOLTAGE LEVELS
Section 1.0 “Device Overview”
Tolerated
 2010 Microchip Technology Inc.
Input
5.5V
V
DD
DD
. Voltage excursions
for more details.
Only V
levels tolerated.
Tolerates input
levels above
V
most standard
logic.
DD
Description
, useful for
DD
input
(1)