XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 21

• Manufacturer Part Number: XR16L570IL24-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
• Manufacturer: Exar Corporation

Specifications of XR16L570IL24-F

• Features: *
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 1.62 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
SEE”RECEIVER” ON PAGE 11.
SEE”TRANSMITTER” ON PAGE 10.
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’.
SEE”PROGRAMMABLE BAUD RATE GENERATOR” ON PAGE 9.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.4
4.4.1
A
A2-A0
DDRESS
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Baud Rate Generator Divisors (DLL and DLM) - Read/Write
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
XOFF1
XOFF2
XON1
XON2
N
EFR
R
AME
EG
6: INTERNAL REGISTERS DESCRIPTION.
RD/WR
W
R
WR
WR
WR
WR
EAD
RITE
/
Enable
B
Auto
CTS
Bit-7
Bit-7
Bit-7
Bit-7
IT
-7
Enable
B
Auto
Bit-6
Bit-6
Bit-6
Bit-6
RTS
IT
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
-6
Enhanced Registers
Special
Select
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
IT
-5
21
MCR[7:5],
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[2]
Enable
B
Bit-4
Bit-4
Bit-4
Bit-4
IT
-4
S
HADED BITS ARE ENABLED WHEN
B
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
-3
B
ware
Soft-
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
IT
-2
B
ware
Soft-
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
IT
-1
EFR B
B
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
IT
-0
XR16L570
IT
-4=1
LCR=0
C
OMMENT
X
BF