XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 3

• Manufacturer Part Number: XR16L570IL24-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
• Manufacturer: Exar Corporation

Specifications of XR16L570IL24-F

• Features: *
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 1.62 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
REV. 1.0.1
PIN DESCRIPTIONS
DATA BUS INTERFACE
MODEM OR SERIAL I/O INTERFACE
DSR#
IOW#
RTS#
CTS#
DTR#
N
IOR#
CS#
INT
RX
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
TX
AME
24-QFN
P
12
13
14
24
23
22
21
20
11
15
16
18
IN
3
2
1
9
6
5
4
-
-
#
32-QFN
P
17
18
19
32
31
30
29
14
12
20
21
24
22
25
IN
5
4
3
1
8
7
6
#
T
I/O
YPE
O
O
O
O
I
I
I
I
I
I
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
the UART during a data bus transaction.
Data bus lines [7:0] (bidirectional).
This input is the read strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed by the address
lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it
on the rising edge.
This input is the write strobe (active low). The falling edge instigates the internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
This input is chip select (active low) to enable the device.
This output is the active high device interrupt output. The output state is defined by
the user through the software setting of MCR[3]. INT is set to the active mode when
MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a
logic 0. See MCR[3].
UART Transmit Data or infrared encoder data. Standard transmit and receive inter-
face is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during
reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when
MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it unconnected.
UART Receive Data or infrared receive data. Normal receive data input must idle at
logic 1 condition. The infrared receiver idles at logic 0.
UART Request-to-Send (active low) or general purpose output. This output must be
asserted prior to using auto RTS flow control, see EFR[6], MCR[1] and IER[6].
UART Clear-to-Send (active low) or general purpose input. It can be used for auto
CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be connected to
VCC when not used.
UART Data-Terminal-Ready (active low) or general purpose output. This pin is not
available in the 24-QFN package.
UART Data-Set-Ready (active low) or general purpose input. This input should be
connected to VCC when not used. This input has no effect on the UART. This pin is
not available in the 24-QFN package.
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
3
D
ESCRIPTION
XR16L570