ISP1507CBS-T NXP Semiconductors, ISP1507CBS-T Datasheet - Page 22

• Manufacturer Part Number: ISP1507CBS-T
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507CBS-T

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: ISP1507CBS,518

NXP Semiconductors
ISP1507C_ISP1507D_1
Product data sheet
Fig 5.
DATA[7:0]
RESET_N
CLOCK
NXT
STP
DIR
Interface behavior with respect to RESET_N
9.3.2 Interface behavior with respect to RESET_N
9.4.1 Driving 5 V on V
9.4.2 Fault detection
9.4 V
Hi-Z (input)
Hi-Z (input)
The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the
ISP1507 will assert DIR. All logic in the ISP1507 will be reset, including the analog
circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;
otherwise undefined behavior may result. When RESET_N is deasserted (HIGH), the DIR
output will deassert (LOW) four or five clock cycles later.
behavior when RESET_N is asserted (LOW), and subsequently deasserted (HIGH). If
RESET_N is not used, it must be connected to V
The ISP1507 supports external 5 V supplies. The ISP1507 can control the external supply
using the active-LOW PSW_N open-drain output pin. To enable the external supply by
driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG_CTRL
register (see
DRV_VBUS bit can be set to any value and will be ignored.
The ISP1507 supports external V
circuit is required for host applications that supply more than 100 mA on V
between 4.75 V to 5.25 V. For low-power applications supplying less than 100 mA, the
V
link can utilize the internal A_VBUS_VLD comparator.
The ISP1507 supports external V
indicator signal. The indicator signal must be connected to the V
the ISP1507 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND
bit in the OTG_CTRL register (see
INTF_CTRL register (see
BUS
BUS
power line can directly be connected to the V
power and fault detection
Section
Hi-Z (link must drive)
Hi-Z (link must drive)
BUS
10.1.4) to logic 1. When the DRV_VBUS_EXT bit is set, the
Rev. 01 — 28 May 2008
Section
BUS
BUS
10.1.3) to logic 1. For details, see
Section
fault detector circuits. An overcurrent detection
fault detector circuits that output a digital fault
ULPI HS USB host and peripheral transceiver
Hi-Z (input)
Hi-Z (input)
10.1.4) and the IND_PASSTHRU bit in the
ISP1507C; ISP1507D
CC(I/O)
BUS
/FAULT pin on the ISP1507 and the
.
Figure 5
BUS
shows the ULPI
/FAULT pin. To enable
Figure
© NXP B.V. 2008. All rights reserved.
BUS
7.
for voltages
004aaa720
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