ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 14

• Manufacturer Part Number: ISP1507B1HNTM
• Manufacturer: STEricsson

Specifications of ISP1507B1HNTM

• Lead Free Status / RoHS Status: Compliant

CD00269905
Product data sheet
8.9.15 NXT
8.9.16 CLOCK
8.9.17 CHIP_SELECT_N
8.9.18 GND
ULPI next data output pin. The ISP1507x1 holds NXT at LOW, by default. When DIR is
LOW and the link is sending data to the ISP1507x1, NXT will be asserted to notify the link
to provide the next data byte. When DIR is at HIGH and the ISP1507x1 is sending data to
the link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is
not used for register read data or the RXCMD status update.
The NXT pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.
For details on NXT usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
A 60 MHz interface clock to synchronize the ULPI bus. The ISP1507x1 provides two
clocking options:
For details on CLOCK usage, refer to UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1.
Active-LOW chip select pin. If CHIP_SELECT_N is not used, it must be connected to
GND. For more information on using CHIP_SELECT_N, see
Global ground signal. To ensure correct operation of the ISP1507x1, GND must be
soldered to the cleanest ground available.
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A crystal attached between the XTAL1 and XTAL2 pins.
A clock driven into the XTAL1 pin, with the XTAL2 pin left floating.
Rev. 03 — 26 July 2010
ISP1507A1; ISP1507B1
ULPI HS USB OTG transceiver
Section
© ST-ERICSSON 2010. All rights reserved.
10.3.3.
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