ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 66
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ISP1507B1HNTM
Manufacturer Part Number
ISP1507B1HNTM
Description
Manufacturer
STEricsson
Datasheet
1.ISP1507B1HNTM.pdf
(78 pages)
Specifications of ISP1507B1HNTM
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Compliant
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Fig 23. Rise time and fall time
Fig 25. Timing of TX_ENABLE to DP and DM
1.8 V
V
V
V
V
0 V
OH
OH
OL
OL
logic
input
differential
data lines
0.9 V
t
HSR
10%
16.1 ULPI timing
, t
FR
t
V
t
PZH
PZL
CRS
, t
LR
90%
ULPI interface timing requirements are given in
synchronous mode only. All timing is measured with respect to the ISP1507x1 CLOCK
pin. All signals are clocked on the rising edge of CLOCK.
Fig 27. ULPI interface timing
CONTROL OUT
CONTROL IN
(DIR, NXT)
DATA OUT
DATA IN
CLOCK
V
V
(8-BIT)
(8-BIT)
OH
OL
(STP)
90%
+ 0.3 V
− 0.3 V
t
HSF
t
t
0.9 V
PHZ
PLZ
, t
10%
FF
, t
LF
t
su(DATA)
t
su(STP)
Rev. 03 — 26 July 2010
004aaa861
004aaa574
t
t
h(STP)
h(DATA)
Fig 24. Timing of TX_DAT and TX_SE0 to DP and DM
Fig 26. Timing of DP and DM to RX_RCV, RX_DP, and
1.8 V
differential
data lines
V
V
0 V
logic input
OH
OL
logic output
0.8 V
2.0 V
V
V
differential
data lines
ISP1507A1; ISP1507B1
OH
OL
RX_DM
0.9 V
V
t
t
CRS
Figure
t
d(DIR)
d(NXT)
d(DATA)
t
PLH(drv)
,
V
t
t
PLH(se)
PLH(rcv)
CRS
27. This timing applies to
0.9 V
ULPI HS USB OTG transceiver
t
t
d(DIR)
d(NXT)
© ST-ERICSSON 2010. All rights reserved.
,
t
PHL(drv)
0.9 V
t
t
V
PHL(rcv)
PHL(se)
CRS
V
004aaa575
004aaa722
004aaa573
CRS
0.9 V
66 of 78
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