ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 74

• Manufacturer Part Number: ISP1507B1HNTM
• Manufacturer: STEricsson

Specifications of ISP1507B1HNTM

• Lead Free Status / RoHS Status: Compliant

22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
Table 11. RXCMD byte format . . . . . . . . . . . . . . . . . . . .26
Table 12. LINESTATE[1:0] encoding for upstream facing
Table 13. LINESTATE[1:0] encoding for downstream facing
Table 14. Encoded V
Table 15. V
Table 16. Encoded USB event signals . . . . . . . . . . . . . .30
Table 17. PHY pipeline delays . . . . . . . . . . . . . . . . . . . .34
Table 18. Link decision times . . . . . . . . . . . . . . . . . . . . .35
Table 19. Immediate register set overview . . . . . . . . . . .48
Table 20. Extended register set overview . . . . . . . . . . . .48
Table 21. VENDOR_ID_LOW - Vendor ID Low register
Table 22. VENDOR_ID_HIGH - Vendor ID High register
Table 23. PRODUCT_ID_LOW - Product ID Low register
Table 24. PRODUCT_ID_HIGH - Product ID High register
Table 25. FUNC_CTRL - Function Control register (address
Table 26. FUNC_CTRL - Function Control register (address
Table 27. INTF_CTRL - Interface Control register (address
Table 28. INTF_CTRL - Interface Control register (address
Table 29. OTG_CTRL - OTG Control register (address R =
Table 30. OTG_CTRL - OTG Control register (address R =
Table 31. USB_INTR_EN_R_E - USB Interrupt Enable
Table 32. USB_INTR_EN_R_E - USB Interrupt Enable
CD00269905
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
ULPI signal description . . . . . . . . . . . . . . . . . .15
Signal mapping during low-power mode . . . . .16
Signal mapping for 6-pin serial mode . . . . . . .17
Signal mapping for 3-pin serial mode . . . . . . .18
Operating states and their corresponding resistor
settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
OTG_CTRL register power control bits . . . . . .25
ports: peripheral . . . . . . . . . . . . . . . . . . . . . . . .27
ports: host . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
applications . . . . . . . . . . . . . . . . . . . . . . . . . . .29
(address R = 00h) bit description . . . . . . . . . . .49
(address R = 01h) bit description . . . . . . . . . . .49
(address R = 02h) bit description . . . . . . . . . . .49
(address R = 03h) bit description . . . . . . . . . . .49
R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit allocation . . . .53
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit description . .53
BUS
indicators in RXCMD required for typical
BUS
voltage state . . . . . . . . . . . . . .28
Rev. 03 — 26 July 2010
Table 33. USB_INTR_EN_F_E - USB Interrupt Enable
Table 34. USB_INTR_EN_F_E - USB Interrupt Enable
Table 35. USB_INTR_STAT - USB Interrupt Status register
Table 36. USB_INTR_STAT - USB Interrupt Status register
Table 37. USB_INTR_L - USB Interrupt Latch register
Table 38. USB_INTR_L - USB Interrupt Latch register
Table 39. DEBUG - Debug register (address R = 15h) bit
Table 40. DEBUG - Debug register (address R = 15h) bit
Table 41. SCRATCH - Scratch register (address R =
Table 42. PWR_CTRL - Power Control register (address
Table 43. PWR_CTRL - Power Control register (address
Table 44. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 45. Recommended operating conditions . . . . . . . 58
Table 46. Static characteristics: supply pins . . . . . . . . . . 59
Table 47. Static characteristics: digital pins . . . . . . . . . . 59
Table 48. Static characteristics: digital pin FAULT . . . . . 60
Table 49. Static characteristics: digital pin PSW_N . . . . 60
Table 50. Static characteristics: analog I/O pins
Table 51. Static characteristics: V
Table 52. Static characteristics: V
Table 53. Static characteristics: ID detection circuit . . . . 62
Table 54. Static characteristics: resistor reference . . . . . 62
Table 55. Dynamic characteristics: reset and clock . . . . 63
Table 56. Dynamic characteristics: digital I/O pins . . . . . 64
Table 57. Dynamic characteristics: analog I/O pins (DP and
Table 58. Recommended list of materials . . . . . . . . . . . . 67
Table 59. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 60. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 73
ISP1507A1; ISP1507B1
DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Falling Edge register (address R = 10h to 12h,
W = 10h, S = 11h, C = 12h) bit allocation . . . . 53
Falling Edge register (address R = 10h to 12h,
W = 10h, S = 11h, C = 12h) bit description . . . 53
(address R = 13h) bit allocation . . . . . . . . . . . 54
(address R = 13h) bit description . . . . . . . . . . 54
(address R = 14h) bit allocation . . . . . . . . . . . 54
(address R = 14h) bit description . . . . . . . . . . 54
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
16h to 18h, W = 16h, S = 17h, C = 18h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ULPI HS USB OTG transceiver
BUS
BUS
© ST-ERICSSON 2010. All rights reserved.
comparators . . . . 62
resistors . . . . . . . . 62
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