AM50DL128CG70I AMD (ADVANCED MICRO DEVICES), AM50DL128CG70I Datasheet - Page 14

• Manufacturer Part Number: AM50DL128CG70I
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM50DL128CG70I

• Lead Free Status / RoHS Status: Supplier Unconfirmed

(Note that this is a more restricted voltage range than
V
within V
mode, but the standby current will be greater. The de-
vice requires standard access time (t
cess when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
ification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
November 7, 2002
CC3
CC5
IH
.) If CE#f and RESET# are held at V
f in the table represents the standby current spec-
f in the table represents the automatic sleep mode
CC
± 0.3 V, the device will be in the standby
CE
) for read ac-
P R E L I M I N A R Y
IH
, but not
RP
ACC
Am50DL128CG
, the
+
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
held at V
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
Algorithms). The system can read data t
RESET# pin returns to V
Refer to the pSRAM AC Characteristics tables for RE-
SET# parameters and to Figure 16 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
READY
IL
but not within V
(during Embedded Algorithms). The
READY
IH
.
IH
SS
, output from the device is
±0.3 V, the standby cur-
(not during Embedded
CC4
SS
±0.3 V, the device
f). If RESET# is
RH
after the
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