AM50DL128CG70I AMD (ADVANCED MICRO DEVICES), AM50DL128CG70I Datasheet - Page 48
AM50DL128CG70I
Manufacturer Part Number
AM50DL128CG70I
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AM50DL128CG70I.pdf
(63 pages)
Specifications of AM50DL128CG70I
Lead Free Status / RoHS Status
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FLASH AC CHARACTERISTICS
Note:
1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
2. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash
November 7, 2002
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Addresses
DQ6/DQ2
WE#
DQ6
DQ2
cycle, and array data read cycle.
device must be held high during this operation.
RY/BY#
CE#f
WE#
OE#
Embedded
Erasing
Enter
Valid Data
t
DH
t
OEH
Erase
Figure 22. Toggle Bit Timings (During Embedded Algorithms)
Suspend
Erase
Erase Suspend
(first read)
Status
Valid
Read
P R E L I M I N A R Y
t
OEPH
Figure 23. DQ2 vs. DQ6
Suspend Program
Enter Erase
Am50DL128CG
t
AHT
t
OE
(second read)
t
ASO
Status
Valid
Suspend
Program
Erase
t
CEPH
t
t
AHT
AS
Erase Suspend
Read
(stops toggling)
Resume
Erase
Status
Valid
Erase
Valid Data
Complete
Erase
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