S71PL129JB0BAW9Z0 Spansion Inc., S71PL129JB0BAW9Z0 Datasheet - Page 133

• Manufacturer Part Number: S71PL129JB0BAW9Z0
• Manufacturer: Spansion Inc.

Specifications of S71PL129JB0BAW9Z0

• Lead Free Status / RoHS Status: Compliant

Notes:
1. A write occurs during the overlap (t
2. t
3. t
4. t
October 28, 2005 S71PL129Jxx_00_A8
with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A
write ends at the earliest transition when CS1# goes high and WE# goes high. The t
write to the end of write.
high.
CW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the end of write to the address change. t
is measured from the CS1# going low to the end of write.
CS1#
CS2
Address
UB#, LB#
WE#
Data in
Data out
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)
A d v a n c e
WP
) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low
S71PL129JC0/S71PL129JB0/S71PL129JA0
t
AS
I n f o r m a t i o n
High-Z
t
t
AW
WR
CW
t
t
WC
WP
t
BW
is applied in case a write ends with CS1# or WE# going
t
DW
Data Valid
t
WR
WP
t
DH
is measured from the beginning of
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