S71PL129JB0BAW9Z0 Spansion Inc., S71PL129JB0BAW9Z0 Datasheet - Page 6

• Manufacturer Part Number: S71PL129JB0BAW9Z0
• Manufacturer: Spansion Inc.

Specifications of S71PL129JB0BAW9Z0

• Lead Free Status / RoHS Status: Compliant

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 63
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .64
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .66
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 75
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 79
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Functional Description . . . . . . . . . . . . . . . . . . . . . 81
4
RY/BY#: Ready/Busy# .......................................................................................58
DQ6: Toggle Bit I ............................................................................................... 58
DQ2: Toggle Bit II .............................................................................................. 60
Reading Toggle Bits DQ6/DQ2 ..................................................................... 60
DQ5: Exceeded Timing Limits ........................................................................ 61
DQ3: Sector Erase Timer ................................................................................. 61
Industrial (I) Devices ......................................................................................... 64
Extended (E) Devices ........................................................................................ 64
Supply Voltages ................................................................................................... 64
Test Conditions .................................................................................................. 66
Switching Waveforms ....................................................................................... 66
VCC RampRate ...................................................................................................67
Read Operations .................................................................................................67
Reset ...................................................................................................................... 69
Erase/Program Operations ............................................................................. 70
Timing Diagrams ...................................................................................................71
Controlled Erase Operations ..........................................................................77
Figure 7. Toggle Bit Algorithm.............................................. 60
Table 14. Write Operation Status ......................................... 62
Figure 8. Maximum Overshoot Waveforms............................. 63
Table 15. CMOS Compatible ................................................ 65
Figure 9. Test Setups......................................................... 66
Table 16. Test Specifications ............................................... 66
Table 17. Key to Switching Waveforms ................................. 66
Figure 10. Input Waveforms and Measurement Levels............. 67
Table 18. Read-Only Operations .......................................... 67
Figure 11. Read Operation Timings ....................................... 68
Figure 12. Page Read Operation Timings ............................... 68
Table 19. Hardware Reset (RESET#) .................................... 69
Figure 13. Reset Timings..................................................... 69
Table 20. Erase and Program Operations .............................. 70
Figure 14. Program Operation Timings .................................. 71
Figure 15. Accelerated Program Timing Diagram .................... 71
Figure 16. Chip/Sector Erase Operation Timings ..................... 72
Figure 17. Back-to-back Read/Write Cycle Timings ................. 73
Figure 18. Data# Polling Timings
(During Embedded Algorithms) ............................................ 73
Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 74
Figure 20. DQ2 vs. DQ6 ...................................................... 74
Table 21. Temporary Sector Unprotect ................................. 75
Figure 21. Temporary Sector Unprotect Timing Diagram.......... 75
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 76
Table 22. Alternate CE# Controlled Erase and
Program Operations ........................................................... 77
Table 23. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ............................................................. 78
Table 24. CE1#/CE2# Timing ............................................. 78
Figure 23. Timing Diagram for Alternating Between CE1# and CE2#
Control ............................................................................. 79
Table 25. Erase And Programming Performance .................... 79
pSRAM Type 6
S71PL129JC0/S71PL129JB0/S71PL129JA0
A d v a n c e
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 81
AC Characteristics and Operating Conditions . 82
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 83
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Functional Description . . . . . . . . . . . . . . . . . . . . . 89
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 89
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 95
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 96
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 97
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 108
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Product Information . . . . . . . . . . . . . . . . . . . . . . 119
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . 120
Read Timings ........................................................................................................84
Write Timings ......................................................................................................86
Deep Power-down Timing ..............................................................................87
Power-on Timing ................................................................................................87
Provisions of Address Skew ............................................................................88
Output Load Circuit ..........................................................................................96
Read Cycle .......................................................................................................... 108
Write Cycle ...........................................................................................................111
Partial Array Self Refresh (PAR) ....................................................................112
Temperature Compensated Refresh (for 64Mb) .....................................113
Deep Sleep Mode ...............................................................................................113
Reduced Memory Size (for 32M and 16M) ..................................................113
Other Mode Register Settings (for 64M) ....................................................113
I n f o r m a t i o n
Figure 24. Read Cycle ........................................................ 84
Figure 25. Page Read Cycle (8 Words Access) ....................... 85
Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)....... 86
Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 87
Figure 28. Deep Power Down Timing .................................... 87
Figure 29. Power-on Timing ................................................ 87
Read ....................................................................................................................88
Figure 30. Read................................................................. 88
Write ..................................................................................................................88
Figure 31. Write ................................................................ 88
Figure 32. Output Load Circuit............................................. 96
Figure 33. Timing of Read Cycle
(CE# = OE# = V
Figure 34. Timing Waveform of Read Cycle
(WE# = ZZ# = V
Figure 35. Timing Waveform of Page Mode Read Cycle
(WE# = ZZ# = V
Figure 36. Timing Waveform of Write Cycle
(WE# Control, ZZ# = V
Figure 37. Timing Waveform of Write Cycle
(CE# Control, ZZ# = V
Figure 38. Timing Waveform of Page Mode Write Cycle
(ZZ# = V
Figure 39. Mode Register .................................................. 114
Figure 40. Mode Register Update Timings (UB#, LB#, OE# are
Don’t Care)..................................................................... 114
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 115
Figure 42. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M)........................................................... 115
IH
) ................................................................... 112
IL
IH
IH
, WE# = ZZ# = V
)......................................................... 109
)......................................................... 110
Type 2 pSRAM
pSRAM Type 1
IH
IH
)................................................. 111
)................................................ 111
S71PL129Jxx_00_A8 October 28, 2005
IH
) .............................. 108