MT47H32M16GC-5E:B Micron Technology Inc, MT47H32M16GC-5E:B Datasheet - Page 122
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MT47H32M16GC-5E:B
Manufacturer Part Number
MT47H32M16GC-5E:B
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H32M16GC-5EB.pdf
(139 pages)
Specifications of MT47H32M16GC-5E:B
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
600ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
160mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
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Figure 71: Self Refresh
PDF: 09005aef82f1e6e2
Rev. M 9/08 EN
DQS#, DQS
Command
Address
ODT 6
CKE 1
CK#
CK 1
DM
DQ
t AOFD/ t AOFPD 6
NOP
T0
t CH
t RP 8
Notes:
Enter self refresh
mode (synchronous)
t CL
REF
10. Upon exiting SELF REFRESH, ODT must remain LOW until
T1
1. Clock must be stable and meeting
2. Self refresh exit is asynchronous; however,
3. CKE must stay HIGH until
4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0,
5.
6. ODT must be disabled and Rtt off (
7.
8. Device must be in the all banks idle state prior to entering self refresh mode.
9. After self refresh has been entered,
refresh mode and at least 1 ×
ing clock edge where CKE HIGH satisfies
may go back LOW after
which allows any nonREAD command.
t
ing self refresh at state T1.
t
refresh.
XSNR is required before any nonREAD command can be applied.
XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
t CK 1
T2
t CKE (MIN) 9
Ta0
t
t CK 1
XSNR is satisfied.
122
t
Exit self refresh
mode (asynchronous)
XSRD is met; however, if self refresh is being re-entered, CKE
t
Ta1
CK prior to exiting self refresh mode.
t
t
CK specifications at least 1 ×
AOFD and
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CKE (MIN) must be satisfied prior to exiting self
t ISXR 2
NOP 4
512Mb: x4, x8, x16 DDR2 SDRAM
t
ISXR.
Ta2
t
XSNR and
t
t CKE 3
AOFPD have been satisfied) prior to enter-
t XSNR 2, 5, 10
NOP 4
Tb0
t
Indicates a break in
time scale
XSRD timing starts at the first ris-
t XSRD 2, 7
t
XSRD is satisfied.
© 2004 Micron Technology, Inc. All rights reserved.
Valid 5
Valid
t
CK after entering self
Tc0
SELF REFRESH
Don’t Care
Valid 7
Valid 5
Td0
t IH
t IH
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