MT36LSDF12872Y-13ED1 Micron Technology Inc, MT36LSDF12872Y-13ED1 Datasheet - Page 12

• Manufacturer Part Number: MT36LSDF12872Y-13ED1
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDF12872Y-13ED1

• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.466A
• Number Of Elements: 36
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Write Burst Mode
Table 7:
Commands
Table 8:
PDF: 09005aef807da15c/Source: 09005aef80f69382
SDF36C64_128x72G.fm - Rev. E 10/05 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
CAS Latency Table
Input register adds one clock in registered mode
SDRAM Command and DQMB Operation Truth Table
CKE is HIGH for all commands shown except SELF REFRESH
Speed
-13E
-133
Notes: 1. A0–A12 provide device row address. BA0, BA1 determine which device bank is made
When M9 = 0, BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
Table 8, provides a quick reference of available commands. This is followed by a written
description of each command. For a more detailed description of commands and opera-
tions, refer to 128Mb or 256Mb SDRAM component data sheet.
2. A0–A9, A11 provide device column address; A10 HIGH enables the auto precharge feature
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
6. A0–A11 (512MB) or A0–A12 (1GB) define the op-code written to the mode register, and
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
active.
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine
which device bank is being read from or written to.
device banks are precharged and BA0, BA1 are “Don’t Care.”
except for CKE.
should be driven LOW.
delay).
512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM
Allowable Operating Clock Frequency (MHz)
CL = 2
≤ 133
≤ 100
CS#
12
H
L
L
L
L
L
L
L
L
–
–
RAS# CAS# WE# DQMB
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
X
X
X
X
X
X
X
H
L
7
7
©2003 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
CL = 3
≤ 143
≤ 133
X
X
X
X
–
–
Commands
High-Z
Active
Active
Valid
DQ
X
X
X
X
X
X
X
Notes
4, 5
1
2
2
3
6
7
7