MT36LSDF12872Y-13ED1 Micron Technology Inc, MT36LSDF12872Y-13ED1 Datasheet - Page 24

• Manufacturer Part Number: MT36LSDF12872Y-13ED1
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDF12872Y-13ED1

• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.466A
• Number Of Elements: 36
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Table 20:
Table 21:
PDF: 09005aef807da15c/Source: 09005aef80f69382
SDF36C64_128x72G.fm - Rev. E 10/05 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current: SCL = SDA = V
Power supply current: SCL clock frequency = 100 KHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
OUT
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between
IN
= 3mA
OUT
= GND to V
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
= GND to V
DD
SCL = 1 and the falling or rising edge of SDA.
write sequence to the end of the EEPROM internal erase/program cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistor, and the EEPROM does not respond to its slave address.
- 0.3V; All other inputs = V
DD
SS
SS
DD
; V
; V
DDSPD
DDSPD
512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM
= +2.3V to +3.6V
= +2.3V
24
TO
SS
or V
+3.6V
t
Symbol
t
t
t
DD
t
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
t
HIGH
LOW
f
WRC
t
t
WRC) is the time from a valid stop condition of a
BUF
SCL
AA
DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
t
R
F
I
I
Symbol
I
CC
CC
V
V
I
V
I
V
CCS
Write
I
Read
LO
DD
OL
LI
IH
IL
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
V
DD
Min
-10
-10
Serial Presence-Detect
-1
3
Max
–
–
–
–
x 0.7
300
400
0.9
0.3
50
10
©2003 Micron Technology, Inc. All rights reserved.
V
V
DD
DD
Max
Units
3.6
0.4
10
10
30
KHz
3
1
ms
+ 0.5
x 0.3
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
Units
Notes
mA
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4