MT36LSDF12872Y-13ED1 Micron Technology Inc, MT36LSDF12872Y-13ED1 Datasheet - Page 9

• Manufacturer Part Number: MT36LSDF12872Y-13ED1
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDF12872Y-13ED1

• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.466A
• Number Of Elements: 36
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Figure 4:
PDF: 09005aef807da15c/Source: 09005aef80f69382
SDF36C64_128x72G.fm - Rev. E 10/05 EN
Mode Register Definition Diagram
block is uniquely selected by A1–A9, A11 when BL = 2; A2–A9, A11 when BL = 4; and by
A3–A9, A11 when BL = 8. The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. Full-page bursts wrap within the page if the
boundary is reached, as shown in Table 6 on page 10.
M8
0
–
M9
512MB Module Address Bus
1GB Module Address Bus
0
1
M7
0
–
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
Programmed Burst Length
Defined
Single Location Access
M6-M0
to ensure compatibility
M11, M10 = “0, 0, 0”
Program
Write Burst Mode
with future devices.
–
12
A12
Reserved
Reserved
Program
11
11
A11
A11
Operating Mode
Standard Operation
All other states reserved
512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM
10
10
A10
A10
WB
WB
9
9
A9
A9
Op Mode
Op Mode
8
8
A8
A8
9
7
7
A7
A7
CAS Latency
CAS Latency
6
6
A6
A6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
5
A5
A5
4
4
A4
A4
M3
BT
BT
0
1
3
3
A3
A3
M2
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
Burst Length
2
2
A2
A2
M1
M5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
A1
Mode Register Definition
0
0
A0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Mode Register (Mx)
Address Bus
Address Bus
Burst Length
©2003 Micron Technology, Inc. All rights reserved.
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8