MT36LSDF12872Y-13ED1 Micron Technology Inc, MT36LSDF12872Y-13ED1 Datasheet - Page 7

• Manufacturer Part Number: MT36LSDF12872Y-13ED1
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDF12872Y-13ED1

• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.466A
• Number Of Elements: 36
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

General Description
PLL and Register Operation
Serial Presence-Detect Operation
PDF: 09005aef807da15c/Source: 09005aef80f69382
SDF36C64_128x72G.fm - Rev. E 10/05 EN
The MT36LSDF6472 and MT36LSDF12872 are high-speed CMOS, dynamic random-
access, 512MB and 1GB memory modules organized in x72 (ECC) configurations.
SDRAM modules use internally configured quad-bank SDRAM devices with a synchro-
nous interface (all signals are registered on the positive edge of clock signal CK).
Read and write accesses to SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank; A0–A11 [512MB] or A0–A12 [1GB], select the device row). The
address bits registered coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
SDRAM modules provide for programmable read or write BL of 1, 2, 4, or 8 locations, or
full page, with a burst terminate option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence.
SDRAM modules use an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one device bank while accessing one of the other three
device banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-
dom-access operation.
SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between device banks in order to hide pre-
charge time, and the capability to randomly change column addresses on each clock
cycle during a burst access. For more information regarding SDRAM operation, refer to
the 128Mb or 256Mb SDRAM component data sheets.
Prior to normal operation, the SDRAM must be initialized. The following sections pro-
vide detailed information covering device initialization, register definition, command
descriptions and device operation.
These modules can be operated in either registered mode (REGE pin HIGH), where the
control/address input signals are latched in the register on one rising clock edge and
sent to the SDRAM devices on the following rising clock edge (data access is delayed by
one clock), or in buffered mode (REGE pin LOW) where the input signals pass through
the register/buffer to the SDRAM devices on the same clock.
A phase-lock loop (PLL) on the modules is used to redrive the clock to the SDRAM
devices to minimize system clock loading. (CK0 is connected to the PLL, and CK1, CK2,
and CK3 are terminated.)
These modules incorporate serial presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and vari-
ous SDRAM organizations and timing parameters. The remaining 128 bytes of storage
512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2003 Micron Technology, Inc. All rights reserved.