PCA9632DP1-T NXP Semiconductors, PCA9632DP1-T Datasheet - Page 13

• Manufacturer Part Number: PCA9632DP1-T
• Description: LED Drivers 4-BIT FM+I2C-BUS LOW POWER LED
• Manufacturer: NXP Semiconductors

Specifications of PCA9632DP1-T

• Number Of Segments: 4
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Pin Count: 8
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 5.5V
• Low Level Output Current: 100000 uA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Supply Current: 150 uA
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant
• Other names: PCA9632DP1,118

NXP Semiconductors
PCA9632_3
Product data sheet
7.3.4 Group duty cycle control, GRPPWM
Table 9.
Legend: * default value.
When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency
signal is superimposed with the 6.25 kHz Individual brightness control signal. GRPPWM
is then used as a global brightness control allowing the LED outputs to be dimmed with
the same value. The value in GRPFREQ is then a ‘don’t care’.
In the group dimming mode (DMBLNK = 0) global brightness for the 4 outputs is
controlled through 16 linear steps from 00h (0 % duty cycle = LED output off) to F0h
(93.75 % duty cycle = maximum brightness). In this mode only the 4 MSBs of the
GRPPWM[7:4] are used. Bits GRPPWM[3:0] are unused.
E.g., if GDC[7:4] = 1111, then duty cycle = 1111 0000 / 256 = 240 / 256 = 93.75 %.
When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a
global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to
10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
In this mode, when GRPFREQ is programmed to provide a blinking with frequency
programmable from 24 Hz to 6 Hz, GRPPWM[7:2] is used to provide 64-step duty cycle
resolution from 0 % to 98.4 %. GRPPWM[1:0] bits are unused.
E.g., if GDC[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %.
When GRPFREQ is programmed to provide a blinking with frequency programmable from
6 Hz to 0.09 Hz (10.73 s), GRPPWM[7:0] is used to provide a 256-step duty cycle
resolution from 0 % to 99.6 %. In this case, all the 8 bits of the GRPPWM register are
used.
E.g., If GDC[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
duty cycle
duty cycle
duty cycle
Address
06h
GRPPWM - Group duty cycle control register (address 06h) bit description
Register
GRPPWM
=
=
=
GDC 7:4 ,0000
---------------------------------------- -
GDC 7:2 ,00
---------------------------------- -
GDC 7:0
-------------------------- -
256
256
256
Bit
7:0
Rev. 03 — 15 July 2008
Symbol
GDC[7:0]
Access Value
R/W
4-bit Fm+ I
1111 1111
2
C-bus low power LED driver
Description
GRPPWM register
PCA9632
© NXP B.V. 2008. All rights reserved.
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