PCA9632DP1-T NXP Semiconductors, PCA9632DP1-T Datasheet - Page 19

• Manufacturer Part Number: PCA9632DP1-T
• Description: LED Drivers 4-BIT FM+I2C-BUS LOW POWER LED
• Manufacturer: NXP Semiconductors

Specifications of PCA9632DP1-T

• Number Of Segments: 4
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Pin Count: 8
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 5.5V
• Low Level Output Current: 100000 uA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Supply Current: 150 uA
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant
• Other names: PCA9632DP1,118

NXP Semiconductors
8. Characteristics of the I
PCA9632_3
Product data sheet
8.1.1 START and STOP conditions
8.1 Bit transfer
8.2 System configuration
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
Fig 11. Bit transfer
Fig 12. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 03 — 15 July 2008
12).
Figure
data valid
data line
stable;
13).
Figure
allowed
change
of data
4-bit Fm+ I
11).
2
C-bus low power LED driver
STOP condition
mba607
P
PCA9632
© NXP B.V. 2008. All rights reserved.
mba608
SDA
SCL
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