LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 91

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Parallel Port
Direct power management is controlled by CR22. Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B3. When set, this bit allows the ECP or EPP logical parallel port blocks
to be placed into powerdown when not being used.
The EPP logic is in powerdown under any of the following conditions:
1.
2.
The ECP logic is in powerdown under any of the following conditions:
1.
2
Exit Auto Powerdown
The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when
the parallel port mode is changed through the configuration registers.
SERIAL IRQ
The LPC47M10x supports the serial interrupt to transmit interrupt information to the host system. The serial
interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
Timing Diagrams for SER_IRQ Cycle
A) Start Frame timing with source sampled a low pulse on IRQ1
Note:
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge
B) Stop Frame Timing with Host using 17 SER_IRQ sampling period.
Note:
Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
EPP is not enabled in the configuration registers.
EPP is not selected through ecr while in ECP mode.
ECP is not enabled in the configuration registers.
SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode.
PCI_CLK
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
hierarchy in a synchronous bridge design.
SER_IRQ
H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
around clock of the Stop Frame.
Driver
PCI_CLK
SER_IRQ
Drive Source
S
FRAME
None
IRQ14
R
T
IRQ1
SL
or
H
S
IRQ15
START
IRQ15
FRAME
Host Controller
START FRAME
H
R
1
T
S
IOCHCK#
R
None
FRAME
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R
T
T
IRQ0 FRAME IRQ1 FRAME
S
None
I
R
2
STOP FRAME
Host Controller
T
STOP
H
S
IRQ1
1
R
R
T
T
IRQ2 FRAME
NEXT CYCLE
S
None
R
START
T
3