LPC47M112-MW Standard Microsystems (SMSC), LPC47M112-MW Datasheet - Page 88

• Manufacturer Part Number: LPC47M112-MW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M112-MW

• Lead Free Status / RoHS Status: Compliant

Enhanced Super I/O Controller with LPC Interface
Datasheet
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
9.
Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct
18.2
ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater
detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional
single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link
and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer
capability.
Vocabulary
The following terms are used in this document:
assert:
forward: Host to Peripheral communication.
reverse: Peripheral to Host communication
SMSC DS – LPC47M112
The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus.
The host initiates an I/O read cycle to the selected EPP register.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal
is valid.
If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a
time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the
cycle.
The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
EPP read cycles, PCD is required to be a low.
Extended Capabilities Parallel Port
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state.
SIGNAL
EPP
nWrite
Address/Data
Interrupt
nWait
nData Strobe
nReset
nAddress
Strobe
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Status
Error
EPP NAME
TYPE
I/O
Table 40 - EPP Pin Descriptions
O
O
O
O
I
I
I
I
I
DATASHEET
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
This signal is active low.
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is
ready for the next transfer.
This signal is active low. It is used to denote data read or write
operation.
This signal is active low. When driven active, the EPP device
is reset to its initial operational mode.
This signal is active low. It is used to denote address read or
write operation.
Same as SPP mode.
Same as SPP mode.
Same as SPP mode.
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EPP DESCRIPTION
It is driven inactive as a positive
Rev. 02-16-07