LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 105

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

Host I/F Data Register
The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard
Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the
Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for
more information.
Host I/F Status Register
The Status register is 8 bits wide.
Table 52 shows the contents of the Status register.
Status Register
This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M14x CPU.
UD
C/D
IBF
OBF
6.13.7
The LPC47M14x Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset
pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR)
and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.
6.13.8
The LPC47M14x has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer to Table 53 for
the effect of each type of reset on the internal registers.
GATEA20 AND KEYBOARD RESET
The LPC47M14x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and
KRESET and Port 92 Fast GateA20 and KRESET.
SMSC DS – LPC47M14X
UD
D7
Writable by LPC47M14x CPU. These bits are user-definable.
(Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 =
command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2 =
0.
(Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register.
Setting this flag activates the LPC47M14x CPU's nIBF (MIRQ) interrupt if enabled. When the LPC47M14x CPU
reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no
output pin associated with this internal signal.
(Output Buffer Full) - This flag is set to whenever the LPC47M14x CPU write to the output data register (DBB).
When the host system reads the output data register, this bit is automatically reset.
External Clock Signal
Default Reset Conditions
UD
D6
UD
D5
Host I/F Status Reg
Host I/F Data Reg
DESCRIPTION
MDAT
KDAT
MCLK
KCLK
UD
Table 52 – Status Register
D4
Table 53 – Resets
N/A: Not Applicable
Page 105
C/D
D3
HARDWARE RESET
(PCI_RESET#)
UD
D2
Low
Low
Low
Low
00H
N/A
IBF
D1
OBF
D0
Rev. 03/19/2001