LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 160

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

Note 1: A logical device will be active and powered up according to the following equation unless otherwise specified:
Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O
Note 3: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Note 4: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device
SMSC DS – LPC47M14X
Interrupt Select
Defaults :
0x70 = 0x00 or 0x06
(Note 3)
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
0x72 = 0x00,
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
DMA Channel Select
Default = 0x02 or 0x04
(Note 4)
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
32-Bit
Configuration
Logical Device
Logical
Configuration
Reserved
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or
clears the other.
map, then read or write is not valid and is ignored.
3 and 5 is 0x04.
LOGICAL DEVICE
REGISTER
Memory
Device
Space
(0xA9-0xDF)
(0xE0-0xFE)
(0x76-0xA8)
(0x70,0x72)
(0x71,0x73)
(0x74,0x75)
ADDRESS
Table 64 – Logical Device Registers
0xFF
0x70 is implemented for each logical device.
Refer to Interrupt Configuration Register
description. Only the keyboard controller uses
Interrupt Select register 0x72. Unused register
(0x72) will ignore writes and return zero when
read.
compatible).
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Only 0x74 is implemented for FDC and Parallel
port.
writes and returns zero when read. Refer to
DMA Channel Configuration.
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Reserved – Vendor Defined (see SMSC
defined
Registers).
Reserved
Page 160
0x75 is not implemented and ignores
Interrupts default to edge high (ISA
Logical
DESCRIPTION
Device
Configuration
STATE
C
C
C
C
C
Rev. 03/19/2001