FDC37C665GT Standard Microsystems (SMSC), FDC37C665GT Datasheet - Page 146

• Manufacturer Part Number: FDC37C665GT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT

• Lead Free Status / RoHS Status: Not Compliant

1. WRITE is controlled by setting the PDIR bit to "1" in the control register before
nADDRSTB
nDATASTB
IOCHRDY
SD<7:0>
PD<7:0>
t10
t11
t12
t13
t15
t19
t20
t21
t22
t23
nWRITE
performing an EPP Read.
t2
t3
t4
t5
t8
A0-A10
nWAIT
PDIR
nIOR
nIOR Deasserted to Command Deasserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to PDATA Hi-Z
Command Asserted to PDATA Valid
nIOR Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
IOCHRDY Deasserted to nIOR Deasserted
nIOR Deasserted to SDATA High-Z (Hold Time)
PData Valid to SDATA Valid
Time Out
Ax Valid to nIOR Asserted
nIOR Deasserted to Ax Invalid
Command Deasserted to nWAIT Deasserted
nIOR Deasserted to nIOW or nIOR Asserted
nIOR Asserted to Command Asserted
t19
FIGURE 16 - EPP 1.7 DATA OR ADDRESS READ CYCLE
Parameter
t23
t8
t3
t5
t15
146
t13
min
10
40
10
40
0
0
0
0
0
0
t10
max
t11
50
40
24
50
40
40
12
55
t2
t20
t12
units
t4
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
t22
t21
Notes